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Valued Contributor III
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zero time loop in state machine

Hello, while working with a design, I am facing zero time loop in VCS. One of my state machine is causing this zero delay loop and after spending some time, looks like the following snippet of code are responsible for this. 

 

// .... state register code 

// always(*) for next state and output logic 

 

case (state) 

state0: begin  

if (start_i == 1) begin 

 

temp = 8'd117;  

 

next_state = state1; 

end else begin 

 

next_state = state0; 

 

end 

end 

state1: begin 

if (end_i != 1) begin 

 

temp = temp + data_i; // *** looks like something is wrong here. If i remove it then VCS doesn't stuck in zero time loop 

if (temp >= 9'd256) begin 

 

temp = temp - 9'd256; 

end 

 

next_state = state2; 

 

end else begin 

 

next_state = state3; 

end 

 

end 

 

 

As you can guess, in each cycle after having start_i == 1 I add input 8 bit data_i with temp and keep doing it.... I know without looking at the full design its hard to tell but I would appreciate if someone can point me to any error/buggy coding style from above code snippet which might be responsible for the error.
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2 Replies
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Valued Contributor III
5 Views

I think, you should use non-blocking assignments ( "<=" instead of "=" ) here and don't mix them.

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Valued Contributor III
5 Views

Yes, I fixed it. Thanks!

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