Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error 10232 - Problem with Qsys generated code...

Altera_Forum
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I have a QSYS based system which includes the Hard PCIe core and some of my own logic to drive it.  

 

The design's targeted at a Cyclone IV GX '22. 

 

When I generate the system in Quartus 11.0 the Qsys system generates and I can build the design OK. There are problems with PCIe interrupt handing in 11.0 so I need to build on a later version. 

 

However if I generate the same Qsys system in 11.1 sp2 then try to build the FPGA I get Error 10232. 

 

It looks like it's the same problem as here... 

 

http://www.alteraforum.com/forum/showthread.php?t=3251 

 

..however this is happening in multiple places in the generated code so the fix given there isn't an option. 

 

Has anyone else seen this or know of a workaround? 

 

Thanks for any pointers, 

 

Nial.
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Altera_Forum
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it's definitely worth filing a Service Request on this issue!

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Altera_Forum
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Hello, 

 

Did you find any answer for this 10232 error please ? 

 

Thx
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Altera_Forum
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--- Quote Start ---  

Hello, 

Did you find any answer for this 10232 error please ? 

Thx 

--- Quote End ---  

 

 

 

Yes, search the forums for 10232 and I have a post in a thread Qsys which explains the solution. 

 

 

Nial.
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