Error 10327: Can't determine definition of operator ""+""

[Altera_Forum]

Hello to everybody, 

could someone tell me what's wrong in the following code?    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity round16to12 is    port   (  a : in std_logic_vector(15 downto 0);  q : out std_logic_vector(11 downto 0)  );  end entity;  architecture beh of round16to12 is  signal roundoff : std_logic_vector(11 downto 0) := (0 => a(3), others => '0'); begin    process(a)  begin line 23: q <= (not( a(15)) & a(14 downto 4)) + roundoff;  end process;   end beh;   The error message is the following: Error (10327): VHDL error at round16to12.vhd(23): can't determine definition of operator ""+"" -- found 0 possible definitions  Thank for your support

[Altera_Forum]

I've also tried making an and between individuos(x) and "00000001", "00000010", "00000100" and so on .... I've got an error can't determine definition of operator and.

[Altera_Forum]

why not post the actual code rather than post an explination. It could be several things wrong, but it will all come down to VHDL's typing rules. 

 You did not explain why you are doing what you are trying to do.

[Altera_Forum]

--- Quote Start ---  why not post the actual code rather than post an explination. It could be several things wrong, but it will all come down to VHDL's typing rules.  You did not explain why you are doing what you are trying to do.  --- Quote End ---     ok, I'm making an easy application of a genethic algorithm with an arbitrary fitness function to select the indivduals(8 bits random unsigned).  The other solution i've tried is the following:   library IEEE; use IEEE.STD_LOGIC_1164.ALL; use Ieee.numeric_std.all;         use work.genetica_type.all;   entity binario_fitness is  Port (   clk : in std_logic;  individuos: in genetica; adaptacao: out fitness; somafitness: out unsigned (7 downto 0)  ); end binario_fitness;     architecture Behavioral of binario_fitness is begin       process (clk) begin If (clk 'event and clk = '1') then   for x in 0 to 49 loop   adaptacao(x) <= (individuos(x) and "00000001")-(individuos(x) and "00000010") +(individuos(x) and "00000100")-(individuos(x) and "00001000")+(individuos(x) and "00010000")- (individuos(x) and "001000000") +(individuos(x) and "01000000")-(individuos(x) and "10000000"); somafitness<=(others=>'0');  end loop;   end if ;   end process;   end Behavioral;

[Altera_Forum]

Thanks for the help. It has been solved in another forum with: 

adaptacao(x) <= ("00"&individuos(x)(0 downto 0)) - ("00"&individuos(x)(1 downto 1)) + ("00"&individuos(x)(2 downto 2)) -("00"&individuos(x)(3 downto 3))+("00"&individuos(x)(4 downto 4)) - ("00"&individuos(x)(5 downto 5)) + ("00"&individuos(x)(6 downto 6))- ("00"&individuos(x)(7 downto 7));

[Altera_Forum]

you realise there are issues with this, because the final result can be -4 to +4. You declared adaptacao as an array of unsigned(2 downto 0), so while this only represents 0 to 7, if the input is 10101010 or 01010101 then apdaptacao will be 100 (+4)

[Altera_Forum]

Hello, 

 I'm getting the same error that is mentioned many times in this topic..  Error (10327): VHDL error at ADD_SUBB.vhd(31): can't determine definition of operator ""+"" -- found 0 possible definitions  This is my code.. What am i doing wrong?  Already many thanks for your help! :)  -- Library Declaration LIBRARY ieee; USE ieee.numeric_std.all; USE ieee.std_logic_1164.all;  -- Entity Declaration entity ADD_SUBB is  port  (  a : in std_logic_vector (3 downto 0); -- Input A  b : in std_logic_vector (3 downto 0); -- Input B  sel : in std_logic; -- ADD/SUB, Go's to mux to choose if it is SUB or ADD.  r : out std_logic_vector (3 downto 0); -- Result of ADD or SUB  ovf : out std_logic; -- Overflow, when result is above 15  sign : out std_logic -- + or -  &nbsp;);  end ADD_SUBB;  -- Architecture Body architecture RTL of ADD_SUBB is signal c : std_logic_vector (3 downto 0); -- sum of adder signal d : std_logic; -- overflow of adder signal e : std_logic_vector (3 downto 0); -- sum of subtractor signal f : std_logic; -- sign bit +/-  Begin  process (a,b) -- Add function.  variable p: std_logic_vector (4 downto 0 );   begin  p := '0' & a + '0' & b;  c <= p(3 downto 0) after 5ns;   d <= p(4) after 5ns;  end process;    process(a,b) -- Sub function.  begin  p := '0' & a - '0' & b;  e <= p(3 downto 0) after 5ns;  f <= p(4) after 5ns;  end process;    process(c,d,e,f,sel) -- Decoder(mux)  begin  if sel = '1' then r <= c; ovf <= d;  else r <= e; sign <= f;  end if;  end process; end architecture;

[Altera_Forum]

a and b are std_logic_vectors. You cannot do arithmatic with them 

you need to convert them to unsigned or signed types before you can do arithmatic. You probably want to declare them as signed or unsigned in the first place, or you will need a lot of type conversion:  p := std_logic_vector( unsigned('0' & a) + unsigned('0' & b) );  if p, a and b were all declared as unsigned: a : unsigned(3 downto 0);  type conversions wouldnt be needed: p := ('0'&a) + ('0'&b);  Btw, why are you using "after" keyword. It is not synthesisable and is for simulation only.

[Altera_Forum]

--- Quote Start ---  a and b are std_logic_vectors. You cannot do arithmatic with them you need to convert them to unsigned or signed types before you can do arithmatic. You probably want to declare them as signed or unsigned in the first place, or you will need a lot of type conversion:  p := std_logic_vector( unsigned('0' & a) + unsigned('0' & b) );  if p, a and b were all declared as unsigned: a : unsigned(3 downto 0);  type conversions wouldnt be needed: p := ('0'&a) + ('0'&b);  Btw, why are you using "after" keyword. It is not synthesisable and is for simulation only.  --- Quote End ---    Thank you! Changed it and now i am not getting the fault anymore ! :)  But what i now get is that it adds an latch on some outputs..  Warning (10631): VHDL Process Statement warning at ADD_SUBB.vhd(44): inferring latch(es) for signal or variable "ovf", which holds its previous value in one or more paths through the process Warning (10631): VHDL Process Statement warning at ADD_SUBB.vhd(44): inferring latch(es) for signal or variable "sign", which holds its previous value in one or more paths through the process  I don't want that in my design.. Why is it doing this? I did give all outputs a path ?  Thank you!   -- Library Declaration LIBRARY ieee; USE ieee.numeric_std.all; USE ieee.std_logic_1164.all;  -- Entity Declaration entity ADD_SUBB is  port  (  a : in std_logic_vector (3 downto 0); -- Input A  b : in std_logic_vector (3 downto 0); -- Input B  sel : in std_logic; -- ADD/SUB, Go's to mux to choose if it is SUB or ADD.  r : out std_logic_vector (3 downto 0); -- Result of ADD or SUB  ovf : out std_logic; -- Overflow, when result is above 15  sign : out std_logic -- + or -  );  end ADD_SUBB;  -- Architecture Body architecture RTL of ADD_SUBB is signal c : std_logic_vector (3 downto 0); -- sum of adder signal d : std_logic; -- overflow of adder signal e : std_logic_vector (3 downto 0); -- sum of subtractor signal f : std_logic; -- sign bit +/-  Begin  process (a,b) -- Add function.  variable p: std_logic_vector (4 downto 0 );   begin  p := std_logic_vector(unsigned('0'&a) + unsigned('0'&b));  c <= p(3 downto 0) after 5ns;   d <= p(4) after 5ns;  end process;    process(a,b) -- Sub function.  variable p: std_logic_vector (4 downto 0 );   begin  p := std_logic_vector(unsigned('0'&a) - unsigned('0'&b));  e <= p(3 downto 0) after 5ns;  f <= p(4) after 5ns;  end process;    process(c,d,e,f,sel) -- Decoder(mux)  begin  if sel = '0' then   r <= c;   ovf <= d;  elsif sel = '1' then   r <= e;   sign <= f;  else  r <= c;  ovf <= d;  sign <= f;  end if;  end process; end architecture;

[Altera_Forum]

In a combinational design you need to care that output signals are set in all branches of a conditional statement. If you review the decoder process, you'll realize that it's not the case for sign and ofv. The error message is clearly explaining the issue, by the way.  

Simply add a default assignment as first process statement, e.g. sign <= '0'; ovf <= '0';

[Altera_Forum]

--- Quote Start ---  In a combinational design you need to care that output signals are set in all branches of a conditional statement. If you review the decoder process, you'll realize that it's not the case for sign and ofv. The error message is clearly explaining the issue, by the way.  Simply add a default assignment as first process statement, e.g. sign <= '0'; ovf <= '0';  --- Quote End ---    Thank you for helping me out! :)