Error (10327): undefined operator ""=""

[Altera_Forum]

Hello guys, 

it's been a really long time for me without coding in VHDL. I need a stepper motor controller for my nios2 based project so i thought it's best to implement it in FPGA which led me to write the code bellow:   library ieee;  use ieee.std_logic_1164.all;  use ieee.std_logic_unsigned.all;   entity stepper_motor_controller is  port ( reset_n, clk, f_hn: in std_logic;  mc: in std_logic_vector (1 downto 0);   steps: out std_logic_vector (3 downto 0));  end entity;   architecture behav of stepper_motor_controller is  signal halffull :std_logic_vector (3 downto 0);  begin  process (reset_n,mc(1),f_hn) begin  if (reset_n = '0') then  halffull <= (others=>'0');  elsif (mc(1) = '0') then  halffull <= (others=>'0');  elsif (f_hn = '0') then  halffull <= "0001";  else halffull <= "0011";  end if;  end process;  process (clk) begin  if (rising_edge(clk)) then  if (mc(0)= '1') then  halffull <= halffull(0) & halffull(3 downto 1); --rotate right  else halffull <= halffull(2 downto 0) & halffull(3); --rotate left  end if;  else halffull <= halffull;  end if;  end process; steps <= halffull;  end architecture;  unexpectingly, i ended up having the following error msg:  error (10327): vhdl error at stepper_motor_controller.vhd(16): can't determine definition of operator ""="" -- found 0 possible definitions  i'll really appretiate it if someone could point out the reason for this error or suggest a modification to get over it  Thx in advance, good day ;)

[Altera_Forum]

Hi anis, 

I saw your code and there are missing single cots (') in the IF statement, like "if (MC(0)= 1)", that should be "if (MC(0)= '1')" because you are comparing a bit and not an integer. Good luck!!

[Altera_Forum]

thx leonardo, the cots are not problem..i've updated the code just to make sure 

ps/ single cots are used for vectores not bits but thx anyway :D

[Altera_Forum]

I don't know, but I always use single cots to bit and double cots to vector. Another thing I saw is that you are attributing a value of a bit to a vector of bits when you do "halffull <= '0';". That is what I am seeing until now.

[Altera_Forum]

here you go, code is updated, error is still driving me crazy :shock:

[Altera_Forum]

Well, I copy your code and run Analysis and Synthesis in my PC changing " for ' where is bit and ' to " where is vector and the only error was that it doesn't recognize the ror command. Where does this error occur during Analysis and Synthesis or during the Fitter?

[Altera_Forum]

the problem occured during compilation of the code. i get over it by taking another working code and changing it line by line to this one (the strangest technique lol). i had the "ror" problem then and it seems to be related to the fact that this operator isn't compatible with std_logic_vectors. so to avoid messing with vectors types i just used concatenation to perform rotate actions which works just fine. 

now i'm debugging the program from some constant drivers issues. thx for your efforts leonardo i owe you one ^^

[Altera_Forum]

Ok!! Good luck!!!

[Altera_Forum]

If I understand right, you have removed the original code which the question title is referring to. Deleting the post completely would be similarly meaningful. 

 Apart from this strange practice, I also wonder you checked the code line by line, although Quartus shows you the line where the error occured?  Now the code is still useless, because it's not generating any output.

[Altera_Forum]

I would also suggest to drop the non standard ieee.std_logic_unsigned.all library and use ieee.numeric_std.all instead with its signed and unsigned types.