Question about FSM registered output logic

[Altera_Forum]

Hello, 

Suppose I've got the following code for registered output logic: ************************** always 'at'(posedge clk) begin  if (state == some_state) begin  output <= a;  end end ************************** I thought I would expect something like the following:  https://www.alteraforum.com/forum/attachment.php?attachmentid=6935   but instead waveform in modelsim was like:  https://www.alteraforum.com/forum/attachment.php?attachmentid=6936   I suspect the reason has something to do with using IF statement, but why? Any suggestion will be appreciated.

[Altera_Forum]

Depends on the exact timing of somestate. If it's set synchronously by clk, the first diagram would be correct.

[Altera_Forum]

--- Quote Start ---  Depends on the exact timing of somestate. If it's set synchronously by clk, the first diagram would be correct.  --- Quote End ---    Transition of state is synchronous by clk, that's why I was confused by the waveform given in modelsim (the bottom figure). Now to fix this (without knowing why) I raise a combinatorial flag at 'somestate', and 'output = a' will be set by this flag sequentially. So far so good. But is this making any difference to the original design after compile ? Thanks!