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entity mult16bit is
generic ( DATA_WIDTH : integer := 16 ); port( a : in std_logic_vector(DATA_WIDTH-2 downto 0); --PARAM b : in std_logic_vector(15 downto 0); --PARAM c : out std_logic_vector((3*DATA_WIDTH)-1 downto 0) ); end mult16bit; architecture Behavioral of mult16bit is signal right : std_logic_vector((DATA_WIDTH)+4-3 downto 0); signal left : std_logic_vector((DATA_WIDTH)+4-3 downto 0); signal left_shifted : std_logic_vector((2*DATA_WIDTH)-2 downto 0); signal new_right : std_logic_vector((2*DATA_WIDTH)-2 downto 0); begin MULTIPLIER_right:entity work.mult8bit port map( a => a(7 downto 0), b => b, o => right ); MULTIPLIER_left:entity work.mult8bit port map( a => a(15 downto 8), b => b, o => left ); left_shifted <= left & "0000000" ; left_shifted <= std_logic_vector("sll"(unsigned(left), 8)); new_right <= "00000000" & right; c <= unsigned(new_right) + unsigned(left_shifted) ; end Behavioral; this is my code and i m getting this error please help me to solve this thanks Error (10349): VHDL Association List error at mult16bit.vhd(41): formal "o" does not exist File: /mult16bit.vhd Line: 41Link Copied
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Shouldn't you be using c instead of o?
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we cannot see the declaration of mult8bit, but I assume "o" does not exist as an output port from that entity.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.all; entity mult16bit is generic ( DATA_WIDTH : integer := 16 ); port( a : in std_logic_vector(DATA_WIDTH-1 downto 0); --PARAM b : in std_logic_vector(7 downto 0); --PARAM c : out std_logic_vector((2*DATA_WIDTH)-1 downto 0) ); end mult16bit; architecture Behavioral of mult16bit is signal right : std_logic_vector((DATA_WIDTH)+4-1 downto 0); signal left : std_logic_vector((DATA_WIDTH)+4-1 downto 0); signal left_shifted : std_logic_vector((2*DATA_WIDTH)-1 downto 0); signal new_right : std_logic_vector((2*DATA_WIDTH)-1 downto 0); begin MULTIPLIER_right:entity work.mult8bit port map( a => a(7 downto 0), b => b, c => right ); MULTIPLIER_left:entity work.mult8bit port map( a => a(15 downto 8), b => b, c => left ); left_shifted <= left & "0000000" ; -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8)); new_right <= "00000000" & right; c <= unsigned(new_right) + unsigned(left_shifted) ; end Behavioral; sir now i m getting this error please help me thanks expression has 20 elements, but must have 16 elements File: /mult16bit.vhd Line: 41 expression has 16 elements, but must have 20 elements File: /mult16bit.vhd Line: 41- Mark as New
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I still cannot see the declaration of mult8bit, but I assume the output (c) is 16 bits.
"Left" and "right" are 20 bits, hence the errors. so either: fix the length of left and right only map the appropriate bits.- Mark as New
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--- Quote Start --- I still cannot see the declaration of mult8bit, but I assume the output (c) is 16 bits. "Left" and "right" are 20 bits, hence the errors. so either: fix the length of left and right only map the appropriate bits. --- Quote End --- thanks sir for your help.
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