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Hi everyone
I need to help for my graduate thesis. I am working on aes 128 cipher and i had a code but i need a simulation and testbench . how can i do them . pls help me . I appretiated for your advice and help I hope I could tell you thanks.Link Copied
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What have you tried so far, and what problems are you having?
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my ports are
entity key_gen is port (roundkey: in STD_LOGIC_VECTOR(127 downto 0); round: in round_type; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end entity key_gen; I need to testbench code for modelsim simulation.- Mark as New
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And whats the problem?
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Why not try writing a testbench yourself, and come back when you have problems?
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i am trying to write but i am not so good. and I have to 2 weeks for project ending.
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--- Quote Start --- i am trying to write but i am not so good. and I have to 2 weeks for project ending. --- Quote End --- Well, have a go, then come back when you are having problems. We can help with problems, not do your work for you.
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You have no "begin" after architecture.
"variable" cannot be used in architectures, they have to be in processes/functions (did you mean signal?)
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