Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I need to help for my graduate thesis. I am working on aes 128 cipher and i had a code but i need a simulation and testbench . how can i do them . pls help me . I appretiated for your advice and help I hope I could tell you thanks.
entity key_gen is port (roundkey: in STD_LOGIC_VECTOR(127 downto 0); round: in round_type; DATAOUT: out STD_LOGIC_VECTOR(127 downto 0)); end entity key_gen; I need to testbench code for modelsim simulation.
I had a aes code but i dont know that is it works correct. I need to testbench code for check my code. can you control my code and faults? I am a beginner at fpga
--- Quote Start --- i am trying to write but i am not so good. and I have to 2 weeks for project ending. --- Quote End --- Well, have a go, then come back when you are having problems. We can help with problems, not do your work for you.
