Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Error 10476

Honored Contributor II

In this code at the time of compilation a 10476 error shows up. The code is: 


-- convertidor BCD a 7 segmentos 

library ieee; 

use ieee.std_logic_1164.all; 


-- definicion de la entidad 


entity convertidor7 is 

port (A: in std_logic_vector (1 downto 0); 

B: in std_logic_vector (1 downto 0); 

C: in std_logic_vector (1 downto 0); 

D: in std_logic_vector (1 downto 0); 

adisplay,bdisplay,cdisplay,ddisplay,edisplay,fdisplay,gdisplay: out std_logic); 

end convertidor7; 


-- definicion de las señales de entrada / salida 


architecture bolean of convertidor7 is 

signal An,Bn,Cn,Dn,anda1_out,anda2_out,anda3_out,anda4_out,andb1_out,andb2_out,andb3_out,andb4_out, 




-- fin de definicion de las señales 

-- inicio de programa principal 




An <= not A(1); 

Bn <= not B(1); 

Cn <= not C(1); 

Dn <= not D(1); 


-- a 


anda1_out <= c and an; <=== this is the error 

anda2_out <= An and B and D; 

anda3_out <= Bn and Cn and Dn; 

anda4_out <= A and Bn and Cn; 


adisplay <= anda1_out or anda2_out or anda3_out or anda4_out; 


-- b  


andb1_out <= An and Bn; 

andb2_out <= An and Cn and Dn; 

andb3_out <= An and C and D; 

andb4_out <= A and Bn and Cn; 


bdisplay <=andb1_out or andb2_out or andb3_out or andb4_out; 


-- c 


andc1_out <= An and B; 

andc2_out <= An and D; 

andc3_out <= Bn and Cn and Dn; 

andc4_out <= A and Bn and Cn; 


cdisplay <= andc1_out or andc2_out or andc3_out or andc4_out, 


-- d 


andd1_out <= An and C and Dn, 

andd2_out <= An and Bn and C; 

andd3_out <= Bn and Cn and Dn; 

andd4_out <= A and Bn and Cn; 

andd5_out <= An and B and Cn and D; 


ddisplay <= andd1_out or andd2_out or andd3_out or andd4_out or andd5_out; 


-- e  


ande1_out <= An and C and Dn; 

ande2_out <= Bn and Cn and Dn; 


edisplay <= ande1_out or ande2_out; 


-- f 


andf1_out <= An and B and Cn; 

andf2_out <= An and Cn and Dn; 

andf3_out <= An and B and Dn; 

andf4_out <= A and Bn and Cn; 


fdisplay <= andf1_out or andf2_out or andf3_out or andf4_out; 


-- g 


andg1_out <= An and C and Dn; 

andg2_out <= An and Bn and C; 

andg3_out <= An and B and Cn; 

andg4_out <= A and Bn and Cn; 


gdisplay <= andg1_out or andg2_out or andg3_out or andg4_out; 


end bolean;  


The error states: 


error (10476): vhdl error at bcd7seg.vhd(34): type of identifier "c" does not agree with its usage as "std_ulogic" type 



Could anybody help me? A do not see why  


0 Kudos
3 Replies
Honored Contributor II

C is a std_logic_vector and anda1_out, An are std_logic

Honored Contributor II

Thank you!

Honored Contributor II

Thank you very much!