error 10327

Altera_Forum · ‎05-31-2018

In this code at the time of compilation a 10327 error shows up. The code is:

- convertidor BCD a7 segmentos

library ieee;

useieee.std_logic_1164.all;

-- definicion de laentidad

entity convertidor7is

port (A: instd_logic;

B: in std_logic;

C: in std_logic;

D: in std_logic;

adisplay,bdisplay,cdisplay,ddisplay,edisplay,fdisplay,gdisplay:out std_logic);

end convertidor7;

-- definicion de lasseñales de entrada / salida

architecture boleanof convertidor7 is

signalAn,Bn,Cn,Dn,anda1_out,anda2_out,anda3_out,anda4_out,andb1_out,andb2_out,andb3_out,andb4_out,

andc1_out,andc2_out,andc3_out,andc4_out,andd1_out,andd2_out,andd3_out,andd4_out,andd5_out,

ande1_out,ande2_out,andf1_out,andf2_out,andf3_out,andf4_out,andg1_out,andg2_out,andg3_out,andg4_out:std_logic;

-- fin de definicionde las señales

-- inicio deprograma principal

begin

An <= not A;

Bn <= not B;

Cn <= not C;

Dn <= not D;

-- a

anda1_out <= Cand An;

anda2_out <= Anand B and D;

anda3_out <= Bnand Cn and Dn;

anda4_out <= Aand Bn and Cn;

adisplay <=anda1_out or anda2_out or anda3_out or anda4_out;

-- b

andb1_out <= Anand Bn;

andb2_out <= Anand Cn and Dn;

andb3_out <= Anand C and D;

andb4_out <= Aand Bn and Cn;

bdisplay<=andb1_out or andb2_out or andb3_out or andb4_out;

-- c

andc1_out <= Anand B;

andc2_out <= Anand D;

andc3_out <= Bnand Cn and Dn;

andc4_out <= Aand Bn and Cn;

cdisplay <=andc1_out or andc2_out or andc3_out or andc4_out,

-- d

andd1_out<= an and c and dn; --- here is the error

andd2_out <= Anand Bn and C;

andd3_out <= Bnand Cn and Dn;

andd4_out <= Aand Bn and Cn;

andd5_out <= Anand B and Cn and D;

ddisplay <=andd1_out or andd2_out or andd3_out or andd4_out or andd5_out;

-- e

ande1_out <= Anand C and Dn;

ande2_out <= Bnand Cn and Dn;

edisplay <=ande1_out or ande2_out;

-- f

andf1_out <= Anand B and Cn;

andf2_out <= Anand Cn and Dn;

andf3_out <= Anand B and Dn;

andf4_out <= Aand Bn and Cn;

fdisplay <=andf1_out or andf2_out or andf3_out or andf4_out;

-- g

andg1_out <= Anand C and Dn;

andg2_out <= Anand Bn and C;

andg3_out <= Anand B and Cn;

andg4_out <= Aand Bn and Cn;

gdisplay <=andg1_out or andg2_out or andg3_out or andg4_out;

end bolean;

the error states:

error(10327): vhdl error at bcd7seg.vhd(61): can't determine definition ofoperator ""<="" -- found 0 possibledefinitions

Could anybody help me? A do not see why

Thanks

Altera_Forum · ‎05-31-2018

You have a comma at the end of the previous line instead of a semicolon.