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Hi,
I generated a IP module from SOPC builder, and added the module source files in my project. When I compile it, I get the following error : Error (10481): VHDL Use Clause error at XXX : design library YYY does not contain primary unit ZZZ My SOPC builder IP modules is in Verilog, and my top-level file is in VHDL. I found in the QIP file that the IP design is mapped to a library, using the "-library" syntax. So I instantiated the IP module mapped to this library name in my top-level, and also declared the same library. In Quartus, I added the QIP file in my project, and also declared the library name in the project librairies. Any idea what can cause this error ? Thanks.Link Copied
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