AHDL -> verilog HDL

[Altera_Forum]

i am currently converting an old AHDL design with swedisch comments :eek: into verilog HDL and the Quartus help doesn't help me much 

 is there anybody who knows AHDL ?? quartus net list viewer and others do not show me how quartus implements the AHDL functionality all primitivs are seperated so not realy a help  the line i am currently trying to understand is this one  adresscounter_b[].ena = bit_puls and (adresscounter_c[]==0 )& p_selnew or we114;  adresscounter_b[].ena  is the enable of a DFF so in verilog this would start with (forget the always ....)  always @ ( .... ) if ( ... here comes the AHDL enable condition .. )  adresscounter_b[] <= ....  normaly the AHDL & is equal to the verilog & whereas# is | but how shall i interprete the "and" and the "or" ? is the above AHDL line  bit_puls and (adresscounter_c[]==0 )& p_selnew or we114 translated into verilog as  bit_puls && ( (adresscounter_c == 0 ) & p_selnew ) || we114  bit_puls is a DFFE p_selnew SRFFE we114 a NODE adresscounter is a DFFE  Any comment greatly welcome.  BTW is there a translater tool ?  Thanks in advance.

[Altera_Forum]

The big X have an AHDL -> VHDL/Verilog converter (what a surprise) 

 The code isnt the most readible though - but then when is generated code readable?  You'll need to download their quartus equivalent, and you're after teh xport utility.

[Altera_Forum]

The 'and' is a primitive but it looks like the author just mixed 'and' and '&'. Likewise for the 'or' and '#'. 

Why would you translate a 'working' module?

[Altera_Forum]

because the FPGA the AHDL is runnng at, is and and tooo expensive and the functionality is now included in a much bigger and much cheaper cyclone beside the nios :-) 

 yes it seems that it is mixed but i wunder if there is some kind of invisible ( ) due to AND instead of &

[Altera_Forum]

Also be careful when translating. AHDL does things implicitly if you're not explicit. 

 for example, if you set the enable in a state machine, then any state where it is not set is not remembered, it is by default set to 0. That also goes for data. If enable is 1, but data is left blank, it goes to 0.

[Altera_Forum]

My observation was that if the AHDL module was working fine there is no need to translate it into another HDL as Quartus II will nicely deal with it. Maybe just put a nice HDL wrapper around it to include in the NIOS environment? 

Tricky is referring to what is the real strength of AHDL: you can build nice state machines where you decide which 'signals' (or 'wires'?) are registered and which not (the ones that have a .clk assignment are), but as Tricky says: beware when translating as you must carefully re-think what was meant by the original author.