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Valued Contributor III
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Error 10500 Syntax Error?

Hi there, 

could anyone please point out what is wrong with my code as I don't see anything that is wrong with it? It won't compile and is giving me error 10500 

 

code: 

 

library ieee; use ieee.std_logic_1164.all; entity sev_seg_deco is port ( SW : in std_logic_vector(2 downto 0); HEX0 : out std_logic_vector(6 downto 0); end sev_seg_deco; architecture behav of sev_seg_deco is begin with SW select HEX0 <= "1110110" when "000", "1111001" when "001", "0111000" when "010", "0111111" when "011", "1000000" when others; end architecture behav; 

 

error codes: 

 

error (10500): vhdl syntax error at sev_seg_deco.vhd(9) near text "end"; expecting an identifier ("end" is a reserved keyword), or "constant", or "file", or "signal", or "variable" 

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning 

Error: Peak virtual memory: 630 megabytes 

Error: Processing ended: Sun May 21 17:52:09 2017 

Error: Elapsed time: 00:00:09 

Error: Total CPU time (on all processors): 00:00:18 

Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning 

 

 

Any assistance is greatly appreciated, thank you
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Valued Contributor III
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port( SW : in std_logic_vector(2 downto 0); HEX0 : out std_logic_vector(6 downto 0) ); end sev_seg_deco;

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Valued Contributor III
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Thank you! I just emailed my lecturer and got the same response, I was looking at that for ages... 

 

--- Quote Start ---  

port( SW : in std_logic_vector(2 downto 0); HEX0 : out std_logic_vector(6 downto 0) ); end sev_seg_deco;  

--- Quote End ---  

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Valued Contributor III
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In case it's not obvious for others reading this, the last port in the port list should not end with a semicolon.

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