Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14953 Discussions

Error (10500): VHDL syntax error at nios2_led.vhd(5) near text "ã"; expecting "end", or "begin", or

beginner
Beginner
467 Views

I use Quartus Prime Lite Edition.I'm having trouble compiling.

I wrote the following code, but I get an error.I don't think the syntax is a problem, but why? Let me know if you understand.

----------

library ieee;
use ieee.std_logic_1164.all;
entity led_press_button_nios2 is
port (
CLK : in std_logic;
button : in std_logic;
LED : out std_logic
);
end led_press_button_nios2;

architecture behavioral of led_press_button_nios2 is
component nios2_system is
port(
button_pio : in std_logic;
clk_clk : in std_logic;
led_pio : out std_logic
);
end component nios2_system;

signal button_wire : std_logic;
signal led_wire : std_logic;
begin
button_wire <= not button;

nios2:nios2_system
port map(
clk_clk => CLK,
button_pio => button_wire,
led_pio => led_wire
);
LED <= not led_wire;
end behavioral;

----------

Error content

----------

Error (10500): VHDL syntax error at nios2_led.vhd(5) near text "ã"; expecting "end", or "begin", or a declaration statement
Error (10500): VHDL syntax error at nios2_led.vhd(5) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(6) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(7) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(8) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(9) near text

Error (10523): Ignored construct Nios2_LED at nios2_led.vhd(4) due to previous errors
Error (10500): VHDL syntax error at nios2_led.vhd(12) near text "ã"; expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at nios2_led.vhd(12) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(13) near text "ã"; expecting "end", or "port", or "generic"
Error (10500): VHDL syntax error at nios2_led.vhd(13) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(14) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(15) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(16) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(17) near text
Error (10500): VHDL syntax error at nios2_led.vhd(18) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(19) near text 
Error (10500): VHDL syntax error at nios2_led.vhd(20) near text
Error (10500): VHDL syntax error at nios2_led.vhd(22) near text 

 

0 Kudos
2 Replies
RRomano001
New Contributor I
452 Views

 Hello, your code as appear here compile hassle free.

Error (10500): VHDL syntax error at nios2_led.vhd(5) near text "ã"; expecting "end", or "begin", or a declaration statement

inspect or delete and rewrite offending lines one at a time

supposing line 5 is after port declaration a forbidden character seem there.

EricMunYew_C_Intel
Moderator
427 Views

Can you try below.


component xxx

  port ();

end component;


Reply