Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Error 10500: expecting if

Altera_Forum
Honored Contributor II
2,726 Views

I just don't understand what the matter is that i always get the same error: 

 

10500 VHDL Syntax error at sec_cnt.vhd(58) near text "process"; expecting "if" 

 

(see in attached code) 

 

 

Im thankful for evey helper :)
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Altera_Forum
Honored Contributor II
1,240 Views

The keyword is elsif, not else if

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Altera_Forum
Honored Contributor II
1,240 Views

Ahh right, that's it :D Thank you 

 

C and VHDL just isn't the same ._.
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Altera_Forum
Honored Contributor II
1,240 Views

Nope. C is a programming language, vhdl is a hardware description language.

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