- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello all,
I am trying to incorporate bitwise operations into a file with an 8 bit carry look ahead adder. I declare the entity doing the operations as a component in the file with the carry look ahead adder. However, when I compile I get the following error:Error (10500): VHDL syntax error at <location> near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at <location> near text "port"; expecting "(", or "'", or "."
If I remove the whole process statement process(ops)
leaving operate: operations port map (a(5 downto 0), b(5 downto 0), opc, ops, opr);
, it compiles fine. I even tried to do the port maps with signals but that still did not help my problem. Can someone figure out what's the issue? library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cla4_add_subtract is
port(a, b: in std_logic_vector(7 downto 0);
cin: in std_logic;
subtract: in std_logic;
sum: out std_logic_vector(7 downto 0);
cout: out std_logic;
ops: in std_logic;
opc: in std_logic_vector(2 downto 0);
opr: out std_logic_vector(5 downto 0);
d1, d2, d3, d4: out std_logic_vector(6 downto 0);
overflow: out std_logic);
end cla4_add_subtract;
architecture cla4_add_subtract_arch of cla4_add_subtract is
component mux2to1
port(
a, b: in std_logic_vector(7 downto 0);
sel: in std_logic;
y: out std_logic_vector(7 downto 0));
end component;
component claFour
port( a, b: in std_logic_vector(7 downto 0);
carryin: in std_logic;
sum: out std_logic_vector(7 downto 0);
cgout, cpout, overflow: out std_logic);
end component;
component operations is
port(
a,b: in std_logic_vector(5 downto 0);
opcode: in std_logic_vector(2 downto 0);
start: in std_logic;
result: out std_logic_vector(5 downto 0)
);
end component;
component binbcd
port(bin : std_logic_vector(7 downto 0);
p: out std_logic_vector(9 downto 0));
end component;
component printOut
port(digit: in std_logic_vector(3 downto 0);
print: out std_logic_vector(6 downto 0));
end component;
signal carry: std_logic;
signal b_not: std_logic_vector(7 downto 0);
signal b_actual: std_logic_vector(7 downto 0);
signal sum_i: std_logic_vector(7 downto 0);
signal result: std_logic_vector(9 downto 0);
signal padder: std_logic_vector(3 downto 0);
signal int : integer;
begin
b_not <= not b;
carry <= cin;
MUX_SUB:
mux2to1
port map (b, b_not, subtract, b_actual);
ADD0:
claFour
port map (a, b_actual, carry, sum_i, cout, open, overflow);
sum <= sum_i;
int <= to_integer(signed(sum_i));
process(int)
begin
if int < 0 then
d4 <= "1111110";
else
d4 <= "1111111";
end if;
end process;
segment:
binbcd
port map(sum_i, result);
padder(3) <= result(8);
padder(2) <= result(9);
padder(1) <= '0';
padder(0) <= '0';
print1: printOut port map (padder(3 downto 0), d1);
print2: printOut port map (result(7 downto 4), d2);
print3: printOut port map (result(3 downto 0), d3);
process(ops)
begin
if ops = '1' then
operate: operations port map (a(5 downto 0), b(5 downto 0), opc, ops, opr);
end if;
end process;
end cla4_add_subtract_arch;
library IEEE;
use IEEE.std_logic_1164.all;
entity printOut is
port(digit:in std_logic_vector(3 downto 0);
print:out std_logic_vector(6 downto 0));
end printOut;
architecture parch of printOut is
begin
process(digit)
begin
case digit is
when "0000"=> print <="0000001"; -- '0'
when "0001"=> print <="1001111"; -- '1'
when "0010"=> print <="0010010"; -- '2'
when "0011"=> print <="0000110"; -- '3'
when "0100"=> print <="1001100"; -- '4'
when "0101"=> print <="0100100"; -- '5'
when "0110"=> print <="0100000"; -- '6'
when "0111"=> print <="0001111"; -- '7'
when "1000"=> print <="0000000"; -- '8'
when "1001"=> print <="0000100"; -- '9'
when others=> print <="1111111";
end case;
end process;
end parch;
Link Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You cannot put a component instantiation in a process.
A component is like a microchip. Putting a port map in a process is like asking a circuit to add/remove a chip while the circuit is running, which is impossible.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page