Error 10500

[Altera_Forum]

Hi, i have problems with my vhdl code.  

This is the code: LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;   ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;   ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;   BEGIN   readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);   registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  D <= (others =>'0');  v <= (others =>'0');  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  D (31 downto 0) <= unsigned(writedata (31 downto 0));  else v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  end if; END PROCESS;   distance : PROCESS (clk,reset) begin  if reset = '0' then  D <= (others =>'0');  elsif clk'event and clk='1' then   D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  else  D <= (others =>'0');  end if; END PROCESS;   tableau_de_bord : PROCESS (clk,reset)  begin  if reset = '0' then  tb <= '0';  elsif clk'event and clk='1' then  tb <= '0' when D < Dmax else   '1' when D > Dmax;  end if; end process;   frein : PROCESS (clk,reset) begin  if reset = '0' then  brake <= '0';  elsif clk'event and clk='1' then  brake <= '0' when tb = '0' else   '1' when tb ='1';-- freinage  end if; END PROCESS;   out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;  And the error : Error (10500): VHDL syntax error at ppp.vhd(61) near text "when"; expecting ";" Error (10500): VHDL syntax error at ppp.vhd(71) near text "when"; expecting ";" Error: Quartus II 32-bit Analyze Current File was unsuccessful. 2 errors, 0 warnings  Error: Peak virtual memory: 329 megabytes  Error: Processing ended: Sun May 25 19:34:03 2014  Error: Elapsed time: 00:00:03  Error: Total CPU time (on all processors): 00:00:03  Help me please it's urgent.

[Altera_Forum]

like that ? 

 LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v);  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  v <= (others =>'0');  tb <= '0';  brake <= '0';  elsif clk'event and clk = '1' then  if chip_select ='1' and write_n = '0' then  if address = '0' then  --D (31 downto 0) <= unsigned(writedata (31 downto 0));  v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  if D > Dmax then  tb <= '0';  elsif D < Dmax then  tb <= '1';  end if;  if tb = '0' then  brake <= '0';  elsif tb = '1' then  brake <= '1';   end if;  end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

this one below compiles but I haven't a clue what is it doing. 

LIBRARY IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; ENTITY brake_var IS port ( clk : in std_logic; reset : in std_logic; chip_select : in std_logic; writedata : in std_logic_vector (31 downto 0); write_n : in std_logic; address : in std_logic; readdata : out std_logic_vector (31 downto 0); out_port1 : out std_logic_vector (7 downto 0); out_port2 : out std_logic_vector (7 downto 0) ); END brake_var; ARCHITECTURE brake_system OF brake_var IS signal D : unsigned (31 downto 0); -- distance d'arrêt signal v : unsigned (31 downto 0); -- vitesse du véhicule signal Dmax : unsigned (31 downto 0); -- vitesse max (danger) signal tb : std_logic; signal brake : std_logic; BEGIN readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v); registers: PROCESS (clk, reset) BEGIN if reset = '0' then D <= (others => '0'); v <= (others =>'0'); tb <= '0'; brake <= '0'; elsif clk'event and clk = '1' then if chip_select ='1' and write_n = '0' then if address = '0' then D(31 downto 0) <= unsigned(writedata (31 downto 0)); v(15 downto 0) <= unsigned(writedata (15 downto 0)); else D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; end if; end if; if D > Dmax then tb <= '0'; elsif D < Dmax then tb <= '1'; end if; if tb = '0' then brake <= '0'; elsif tb = '1' then brake <= '1'; end if; end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

and simplified as below. read my comments please. 

LIBRARY IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; ENTITY brake_var IS port ( clk : in std_logic; reset : in std_logic; chip_select : in std_logic; writedata : in std_logic_vector (31 downto 0); write_n : in std_logic; address : in std_logic; readdata : out std_logic_vector (31 downto 0); out_port1 : out std_logic_vector (7 downto 0); out_port2 : out std_logic_vector (7 downto 0) ); END brake_var; ARCHITECTURE brake_system OF brake_var IS signal D : unsigned (31 downto 0); -- distance d'arrêt signal v : unsigned (31 downto 0); -- vitesse du véhicule signal Dmax : unsigned (31 downto 0); -- vitesse max (danger) signal tb : std_logic; signal brake : std_logic; BEGIN readdata <= std_logic_vector(D) when address = '0' else std_logic_vector(v); registers: PROCESS (clk, reset) BEGIN if reset = '0' then D <= (others => '0'); v <= (others =>'0'); tb <= '0'; elsif clk'event and clk = '1' then if chip_select ='1' and write_n = '0' then if address = '0' then D <= unsigned(writedata); v(15 downto 0) <= unsigned(writedata (15 downto 0)); -- what about v(31:16) -- so v takes same data as D but for 16 LSBs? else D <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100; end if; end if; if D > Dmax then tb <= '0'; else tb <= '1'; end if; end if; END PROCESS; brake <= tb; -- ? out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

i changed like that : 

LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(v) when address = '0';  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  v <= (others =>'0');  tb <= '0';  brake <= '0';  elsif clk'event and clk = '1' then  D(31 downto 0) <= (v(15 downto 0)*3)/10 + (v(15 downto 0)*v(15 downto 0))/100;  if chip_select ='1' and write_n = '0' then  if address = '0' then  v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  if D > Dmax then  tb <= '0';  elsif D < Dmax then  tb <= '1';  end if;  if tb = '0' then  brake <= '0';  elsif tb = '1' then  brake <= '1';   end if;    end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;

[Altera_Forum]

got 3 critical errors  

Critical Warning (332148): Timing requirements not met Critical Warning (332148): Timing requirements not met Critical Warning (332148): Timing requirements not met

[Altera_Forum]

so your velocity is actually 16 bits coming when address is 0. 

Then you compute D from it (rather than acquire it from read data.Looks like some braking possible.  The main bottleneck to timing is your divider and multipliers in one single algebra.  You can't do algebra in code. Moreover have you got sdc file for timing constraints so that the tool knows about your speed.

[Altera_Forum]

what sould i do to calculate Distance D then ?

[Altera_Forum]

v*3 can be converted to addition (v+v+v). 

v*v keep it get each one prrior to division e.g. res1 <= v+v+v; res2 <= v*v  convert division to multiplication (optional) since it is divide by constant i.e. scale 10 (or 100) so that it becomes power of 2. If I multiply 10 * 2^15/10 I get 2^15 so use 2^15/10 (i.e. 3277) as mult factor then discard 15 lsbs from result.

[Altera_Forum]

also notice you can rearrange formual as below if you wish: 

  (v+v+v + v*v/10)/10;  or  (v*30 + v*v)/100;  then do division as I explained but v should be declared as 16 bits (not 32 bits)

[Altera_Forum]

LIBRARY IEEE; 

use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use ieee.numeric_std.all;  ENTITY brake_var IS  port (  clk : in std_logic;   reset : in std_logic;   chip_select : in std_logic;  writedata : in std_logic_vector (31 downto 0);  write_n : in std_logic;  address : in std_logic;  readdata : out std_logic_vector (31 downto 0);  out_port1 : out std_logic_vector (7 downto 0);  out_port2 : out std_logic_vector (7 downto 0)); END brake_var;  ARCHITECTURE brake_system OF brake_var IS  signal D : unsigned (31 downto 0); -- distance d'arrêt  signal v : unsigned (31 downto 0); -- vitesse du véhicule   signal Dmax : unsigned (31 downto 0); -- vitesse max (danger)  signal tb : std_logic;  signal brake : std_logic;  BEGIN  readdata <= std_logic_vector(v) when address = '0';  registers: PROCESS (clk, reset) BEGIN  if reset = '0' then  v <= (others =>'0');  tb <= '0';  brake <= '0';  elsif clk'event and clk = '1' then  D(31 downto 0) <= (v(15 downto 0)+v(15 downto 0)+v(15 downto 0))/10 + (v(15 downto 0)*v(15 downto 0))/100;  if chip_select ='1' and write_n = '0' then  if address = '0' then  v (15 downto 0) <= unsigned(writedata (15 downto 0));  end if;  end if;  if D > Dmax then  tb <= '0';  elsif D < Dmax then  tb <= '1';  end if;  if tb = '0' then  brake <= '0';  elsif tb = '1' then  brake <= '1';   end if;    end if; END PROCESS; out_port1 <= (others=> tb); out_port2 <= (others=> brake); END brake_system ;  gave me the same 3 critcal warnings ?  how to convert from division to multiplication in my situation ?

[Altera_Forum]

Before this diving, do you have sdc file for timing constraints?  

 I think best formula for you is this: D = (v*30 + v*v)/100  two multipliers to get result then one mult for division by 100. multiply result by 32768/100 i.e. by 328 then discard 15 lsbs from result of mult

[Altera_Forum]

yes i have this sdc file : 

 create_clock -name {CLOCK_50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {CLOCK_50}]  derive_pll_clocks  derive_clock_uncertainty  It removed 3 critical warnings but those 3 critical warnings persist:  Critical Warning (332148): Timing requirements not met Critical Warning (332148): Timing requirements not met Critical Warning (332148): Timing requirements not met  I modified D like you said.

[Altera_Forum]

1) why v is 32 bits when you only deal with 16 bits? 

2) did you convert division to mult

[Altera_Forum]

i changed v to 16  

and honestly i don't know how to change division :/

[Altera_Forum]

well division is obviously just division but you can convert it to mult/div by truncation i.e. once you get v*30 + v*v result then just do the following: 

multiply result by 328 discard 15 lsbs done

[Altera_Forum]

well multiply result by 328 is clear but  

what how to discard 15 lsbs ?

[Altera_Forum]

--- Quote Start ---  well multiply result by 328 is clear but  what how to discard 15 lsbs ?  --- Quote End ---    result_divided <= result(n downto 15);  I probably will have nightmares of car braking failure tonight...

[Altera_Forum]

hahahahahaha :p :p  

sir we still students :)  so it should be like this ?  result<=(v*30 + v*v)*328 ; result_divided <= result (31 down to 15)

[Altera_Forum]

--- Quote Start ---  hahahahahaha :p :p  sir we still students :)  so it should be like this ?  result<=(v*30 + v*v)*328 ; result_divided <= result (31 down to 15)  --- Quote End ---    correct. if you still get timing violation then break it up into stages: res1 <= v*30; -- 16 bits * 5 bits => 21 bits res2 <= v*v; -- 16 bits * 16 bits => 32 bits res3 <= res1 + res2; -- 21 bits + 32 bits => 33 bits res4 <= res3 *328; -- 33 bits * 9 bits => 42 bits D <= res4(41 downto 15); -- 27 bits only so according to this D needs only be 27 bits (if I my math is right)

[Altera_Forum]

or i'm wrong? i don't know i'm really confused :( 

excuse me

[Altera_Forum]

and for result type ? it should be 32 ?