Error (10818): (does not hold its value outside the clock edge)

[Altera_Forum]

Hello, 

 I am trying to build a pulse counter that shoud be connected to an external switch and count the times the user push the button. moreover i need to output: result,result+1,result +2.    i have written the next code and it works graet on model sim but quartus dosent like it, i an getting the error: Error (10818): Can't infer register for "q2_int[X]" at counter.vhd(32) because it does not hold its value outside the clock edge.   for every bit, someone has an idea how to solve it?   the code is:     --- Quote Start ---  library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all;    entity counter is port ( load : in std_logic;  q,q1,q2 : buffer std_logic_vector (4 downto 0));  end entity; architecture rtl of counter is signal q_int : std_logic_vector (4 downto 0):="00000"; signal q1_int : std_logic_vector (4 downto 0):="00000"; signal q2_int : std_logic_vector (4 downto 0):="00000"; begin process (load,q_int) begin if (q_int="00000") then q<="LLLLL"; q1_int<="LLLLH"; q2_int<="LLLHL"; else   end if; if (rising_edge(load)) then q_int <= q_int + 1;   q1_int<=q1_int + 1;   q2_int<=q2_int + 1; end if; end process; q <= q_int;  q1 <= q1_int; q2 <= q2_int;  end rtl;   --- Quote End ---     thanks alot Pini Sberro

[Altera_Forum]

The recommended way of writing a process that can be synthesized is the following: 

process(clock,reset) begin if (reset = '1') then -- reset conditions elsif (rising_edge(clock)) then -- clocked operations end if; end process;The reset part is optional, but recommended.  I think that in your case the synthesizer is confused by your first if in the process and doesn't know what to do with it. It isn't a reset condition, and you are assigning signal values outside of a clock edge. You should change your first part as a real reset condition, or scrap it and give correct initial values to q_int, q1_int and q2_int. You could also keep only one counter and assign its value +1 or +2 to the correct output. You shouldn't need to use the L and H values if you do everything inside the clocked part of the process.

[Altera_Forum]

Basically there are 2 problems: 

 1. It thinks "load" is a clock. On the edge of load, Q_int is updated along with Q1_int and Q2_int  2. Now that Q_int has changed, it changes Q1 and Q2 int to fixed values, so now these things that were clocked, are no longer clocked.  Now, because you dont have a clock - you dont have to do your logic inside a process. But I think you really could use a clock, like Daixiwen suggests.  One big issue though, appears to be that you're trying to write the code without understanding the hardware that you're describing.

[Altera_Forum]

Thank you very much. 

its working!   Tricky, about ur comment: " appears to be that you're trying to write the code without understanding the hardware that you're describing " it was very usfull for me so thanks again

[Altera_Forum]

I am having the same problem too - Error 10818 (does not hold its value outside the clock edge) and 10822 (couldn't implement registers for assignment on this clock edge) but i cant understand what changes do i need to do. 

 I am trying to build a Counter that count the time user successfully catches a number 8. If it is, then a logic '1' will be sent out and a signal will record the times of success events and sent out too.  I have another question is "can i use rising_edge to detect any change of logic value for any time of signal ? std_logic / unsigned / integer .. etc ....  Here is the code    --- Quote Start ---   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;  entity catch is  port (  PUSH : in std_logic;  COMP : in unsigned(3 downto 0);  RST : in std_logic;  INC_FREQ : out integer range 1 to 10;  SCORE_COUNT : out std_logic  ); end catch;   architecture catch_arch of catch is   signal var_INC_FreQ : integer range 1 to 10;    begin     process (RST,PUSH,COMP)     begin    if RST = '0' then    var_INC_FREQ <= 1;    elsif rising_edge(PUSH) then    if COMP = 8 then    SCORE_COUNT <= '1';    var_INC_FREQ <= var_INC_FREQ + 1;    end if;     else    SCORE_COUNT <= '0';    end if;    end process;    INC_FREQ <= var_INC_FREQ;    end catch_arch;       --- Quote End ---    Thanks alot !

[Altera_Forum]

Remove the Else from the reset and clock condition.

[Altera_Forum]

Thank you for the help, 

 sincerely ,   Katon