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vriable length counter

Altera_Forum
Honored Contributor II
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hello, 

im trying to do a simple morsecode : 

 

 

library ieee; 

use ieee.std_logic_1164.all; 

entity morse is  

port ( sw : in std_logic_vector(2 downto 0); 

e : in std_logic; 

clock : in std_logic; 

led : out std_logic_vector(6 downto 0)); 

 

end morse; 

architecture behavioral of morse is 

signal clk :std_logic:='0'; 

signal sr : std_logic_vector(15 downto 0):="0000000000000000"; 

signal n : integer:=0; 

begin 

 

halfsecclk : process(clock) 

variable count : integer :=0; 

begin 

if clock'event and clock='1' then 

count:=count + 1; 

if count = 2 then 

count :=0; 

clk <= not clk; 

end if; 

end if; 

end process; 

 

muxes : process(e) 

begin 

if e'event and e='0' then 

case sw is 

when "000" => 

sr <= "0000000000011101"; 

n <=6 ; 

when "001" => 

sr <= "0000000101010111"; 

n <=10 ; 

when "010" => 

sr <= "0000010111010111"; 

n <= 12; 

when "011" => 

sr <= "0000000001010111"; 

n <= 8; 

when "100" => 

sr <= "0000000000000001"; 

n <= 2; 

when "101" => 

sr <= "0000000101110101"; 

n <= 10; 

when "110" => 

sr <= "0000000101110111"; 

n <= 10; 

when "111" => 

sr <= "0000000001010101"; 

n <= 8; 

when others => null; 

end case; 

end if; 

end process; 

 

counter : process(clk) 

variable cnt : integer:=0; 

begin 

if rising_edge(clk) then 

 

if sr(0)='0' then 

led <= "1111111"; 

elsif sr(0)='1' then 

led <= "0111111"; 

end if; 

 

sr<="0" & sr(15 downto 1); 

 

end if; 

end process; 

 

end behavioral; 

 

 

what i faild to do is to make the counter process shift the (sr) shift register by (n) times then stop and waits for the next value of sw is entered, i have tried many ideas but it didnt worked as i want it to. 

 

any suggestions please ? 

 

thanks in advance
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Altera_Forum
Honored Contributor II
1,001 Views

 

--- Quote Start ---  

what i faild to do is to make the counter process shift the (sr) shift register by (n) times then stop and waits for the next value of sw is entered, i have tried many ideas but it didnt worked as i want it to. 

 

any suggestions please ? 

--- Quote End ---  

 

 

- Did you simulate the design? If so, what were the results? If not, get one and try it.  

- What else did you try? What didn't work out as you wanted it to? 

 

Kevin Jennings
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Altera_Forum
Honored Contributor II
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I'll try to explain more on what i want , depending on the input (sw) the register (sr) will assigned a collection of bits, also the signal (n) will be assigned an integer value which is the number of bits in the register, all of this will happen in the first process. 

 

in the second process which is clocked i want it to shift the (sr) register for each rising edge clock (n) times. 

 

here is what I've done: 

 

counter : process(clk) 

begin 

if rising_edge(clk) then 

if n/=0 then 

if sr(0)='0' then 

led <= "1111111"; 

elsif sr(0)='1' then 

led <= "0111111"; 

end if; 

n<=n-1; 

sr<="0" & sr(15 downto 1); 

end if; 

end if; 

end process; 

 

end behavioral; 

 

It's totaly wrong since two processes driving sr and n. 

 

I know what I've done is stuped but I'm new to the vhdl and i came from another enviroment.
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Altera_Forum
Honored Contributor II
1,001 Views

 

--- Quote Start ---  

I'll try to explain more on what i want 

--- Quote End ---  

 

 

I would prefer that you answer the questions I posed instead...repeated here since they are still necessary. 

- Did you simulate the design? If so, what were the results? If not, get one and try it.  

- What else did you try? What didn't work out as you wanted it to? 

 

 

--- Quote Start ---  

 

depending on the input (sw) the register (sr) will assigned a collection of bits, also the signal (n) will be assigned an integer value which is the number of bits in the register, all of this will happen in the first process. 

 

in the second process which is clocked i want it to shift the (sr) register for each rising edge clock (n) times. 

 

here is what I've done: 

<snip of partial code> 

 

It's totaly wrong since two processes driving sr and n. 

 

--- Quote End ---  

 

 

OK, so you know what the problem is, you have two processes each driving a couple of signals...one would think then you know what to do which is to combine them into one process (hint: that's the answer) 

 

 

--- Quote Start ---  

I know what I've done is stuped but I'm new to the vhdl and i came from another enviroment. 

--- Quote End ---  

 

It sounds like you know what the problem is, you can't have two drivers for one signal. So what is your question? 

 

Kevin Jennings
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Altera_Forum
Honored Contributor II
1,001 Views

I've got it, thank you K J :)

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Altera_Forum
Honored Contributor II
1,001 Views

can you post your final morse code here? I am trying to do something similar. but cant figure it out 

 

thanks :)
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