Error (10822): couldn't implement registers for assignments on this clock edge

[Altera_Forum]

Hi people, 

 Can you please help me out with the following problem:  I try to increment a signal from the state machine at the rising edge of the clock but it gives me the error: Error (10822): HDL error at Deserializer.vhd(131): couldn't implement registers for assignments on this clock edge   Here is the code:   library ieee;use ieee.std_logic_1164.all; use ieee.numeric_std.all; -------------------------------------- entity Deserializer is port( reset, serialin, clk, enable : in std_logic; bustofft,sink_imag : out std_logic_vector(11 downto 0); led1, led2, clkadc,cs : out std_logic ); end entity; -------------------------------------- architecture implementation of Deserializer is --component flip_flop is --port ( -- clk, reset,enable : in std_logic; -- countink : in integer range 0 to 99; -- countoutk : out integer range 0 to 99 -- ); --end component; -- Signals & Variables -- signal cyclecounter : integer range 0 to 15:=0; signal done : std_logic; signal internalbus : std_logic_vector(11 downto 0); ------------------------------------------------------------------- -- state definitions and signals ---------------------------------- ------------------------------------------------------------------- type state is ( Idle, Startadc, Listen, Talk ); signal present_state, next_state: state; ---------------------------------------------------------------------- --PORTMAPS------------------------------------------------------------ ---------------------------------------------------------------------- begin ------------------------------------------------------------------ -- sequential part of the statemachine ---------------------------- ------------------------------------------------------------------- process(reset, clk, next_state) begin if (reset = '1') then present_state <= Idle; elsif (rising_edge(clk)) then present_state <= next_state; end if; end process; process(present_state,next_state, enable, cyclecounter,done) begin case present_state is when Idle => if enable ='1' then next_state <= Startadc; else next_state <=Idle; end if; when Startadc => if (cyclecounter >= 2) then next_state <= Listen; else next_state <=Startadc; end if; when Listen => if cyclecounter >= 14 then next_state <= Talk; else next_state <=Listen; end if; when Talk => if done = '1' then next_state <= Idle; else next_state <= Talk; end if; end case; end process; process(present_state,clk,cyclecounter,done) begin case present_state is when idle=> cs<='1'; done<='0'; cyclecounter<=0; when startadc=> cs<='0'; done<='0'; if (rising_edge(clk)) then cyclecounter<= cyclecounter+1; end if; when listen => cs<='0'; if(rising_edge(clk)) then cyclecounter <= cyclecounter + 1; internalbus(cyclecounter-3) <= serialin; else end if; when talk => cs<='0'; done<='1'; bustofft<=internalbus; end case; end process; end architecture;

[Altera_Forum]

--- Quote Start ---  Hi people,  Can you please help me out with the following problem:  I try to increment a signal from the state machine at the rising edge of the clock but it gives me the error: Error (10822): HDL error at Deserializer.vhd(131): couldn't implement registers for assignments on this clock edge   Here is the code:    <snip> process(present_state,clk,cyclecounter,done) begin case present_state is when idle=> cs<='1'; done<='0'; cyclecounter<=0; when startadc=> cs<='0'; done<='0'; if (rising_edge(clk)) then cyclecounter<= cyclecounter+1; end if; when listen => cs<='0'; if(rising_edge(clk)) then cyclecounter <= cyclecounter + 1; internalbus(cyclecounter-3) <= serialin; else end if; when talk => cs<='0'; done<='1'; bustofft<=internalbus; end case; end process; <snip>  --- Quote End ---    The highlighted 'if' statements are not correct. The format of a clocked process must one of the following two forms: process(clk) begin if rising_edge(clk) then -- Or you can use falling_edge ... end if; end process; process(clk, reset) begin if reset = '1' then ... elsif rising_edge(clk) then -- Again, you can use falling_edge ... end if; end process;  Your process is not of those forms, the 'if rising_edge...' is buried down inside a case statement. It must be part of the outermost statement.  Kevin Jennings

[Altera_Forum]

it seems like the synthesis got confused when you put asynchronous signals and synchronous signals (registers) under the same process. try putting the synchronous part in a separate process, where it should be in this form: 

  process(clk) begin if rising_edge(clk) then ... end if; end

[Altera_Forum]

Thank you guys! You're advice helped me! 

 Now i'm dealing with another problem. I order to let a ADC work which I have bought, I have to output 3.2mhz to this chip. The FPGA board I Have (DE1) has a 50mhz, 27mhz and 24mhz oscillator. Now I checkt out the PLL megacorefunction, but the wizard will not let me downclock the frequency to anything below 12 mhz.  You guys can clarify that?  Thanks in advance!!

[Altera_Forum]

--- Quote Start ---  Thank you guys! You're advice helped me!  Now i'm dealing with another problem. I order to let a ADC work which I have bought, I have to output 3.2mhz to this chip. The FPGA board I Have (DE1) has a 50mhz, 27mhz and 24mhz oscillator. Now I checkt out the PLL megacorefunction, but the wizard will not let me downclock the frequency to anything below 12 mhz.  You guys can clarify that?  Thanks in advance!!  --- Quote End ---    One option is to generate 32MHz from PLL then divide it by 10 in logic and send it to ADC provided you control timing and lucky with jitter.

[Altera_Forum]

I believe one possible technique of generating good quality clock from fpga is using the DDRIO_out feature. Though it is meant for high speed applications but you may try see its benefits and tell us. I can imagine several ways to exploit this feature. For example you can clock the DDRIO_out with 32MHz clockenabled with your 3.2MHz signal then send '1' on rising edge and '0' on falling edge (if an ADC accepts this sort of duty cycle 1:10) 

 Or clock the DDRIO_out with 32MHz enabled always but send your 3.2MHz signal to DDRIO_out as data on both rising edge and falling edge giving 50:50 duty cycle.

[Altera_Forum]

Thanks again for the tips guys! It worked out!  

 Merry Christmas to everybody.

[Altera_Forum]

--- Quote Start ---  Thank you guys! You're advice helped me!  Now i'm dealing with another problem. I order to let a ADC work which I have bought, I have to output 3.2mhz to this chip. The FPGA board I Have (DE1) has a 50mhz, 27mhz and 24mhz oscillator. Now I checkt out the PLL megacorefunction, but the wizard will not let me downclock the frequency to anything below 12 mhz.  --- Quote End ---    Let me jump ahead. Once you get the clock to the ADC running, presumably the next task you will have is to collect data from that ADC. I'm also presuming that your FPGA design is to be running off of one of the above mentioned clocks. If that's the path you're going down , then the best advice would be to generate the 3.2 MHz synchronously with the FPGA's system clock. Towards that end...  3.2 MHz = 15.625 clocks from the 50 MHz clock which suggests the following implementation: - Generate a counter that counts from 0 to 15 which will give you a 3.3 MHz clock (off a bit, but no jitter) - Phase accumulator implementation which will have jitter but will give you 3.2 MHz  3.2 MHz = 7.5 clocks from the 24 MHz clock which suggests the following implementation: - Put 24 MHz into a PLL to generate 48 MHz output which will then be the main FPGA clock - Create a counter that counts from 0 to 14 and then rolls over back to 0. Choose any value you want to be the count that causes the rising edge; the falling edge would be at the count that is 7 or 8 away. Frequency will be 3.2 MHz, no jitter, duty cycle will not be exactly 50% but that is generally not a concern, but check the specs for your ADC for any requirements in that regard.  Example code (not tested)  process(clk48mhz) begin if rising_edge(clk48mhz) then if (Reset = '1') or (Counter = 14) then Counter <= 0; else Counter <= Counter + 1; end if; if (Counter = 5) then -- 5 is arbitrary Clk3_2mhz <= '1'; elsif (Counter = 5+7) then Clk3_2mhz <= '0'; end if; end if; end process;  Assuming that the ADC data is to be sampled at the 'rising edge' of the 3.2 MHz clock, then this corresponds to a counter value of 5 in the above sample so you would have this...   if rising_edge(clk48mhz) then if (Counter = 5) then -- The value 5 here corresponds to the rising edge generated in the previous process. Sampled_ADC_Data <= ADC_Data; end if; end if; Bottom line is to decide on what your overall design needs to be and select the appropriate clock to work with. Try to have the entire design clocked by that clock. Failure to follow that advice will result in your design having multiple clocks which will result in clock domain crossings which will then lead you to having to tackle issues that I suspect you are not quite ready to tackle at this point.  Kevin Jennings

[Altera_Forum]

Hey guys! Hope you all had a great holiday! 

 I'm back on the project and got these things working so far: Serial ADC output to bus, bus to a FIFO and when the FIFO is filled up the FFT starts reading it. There is one thing I am not sure about.  I can't figure out what dataformat the ADC gives. What happens now is that I just put this 12bit serial output in a buffer en then let the Fast Fourier Transform read it. But in the manual of the FFT there is written that it needs "real" input data.  Is it possible to just typecast this ADC output to a "real" format?

[Altera_Forum]

Typecasting in VHDL is not about real implementation, because at the end of the day the data is still a load of bits, whatever "type" it is in VHDL - its what the data format is in the real world that matters. You need to read the ADC data sheet to see the data format - most likely 1 of 3 things 

1. Unsigned integer 2. Signed integer 3. An offset unsigned number (so 0 is at 2^11)  Also, the FFT will not use a "real" type, it will use either integer, fixed or floating point (probably fixed, which is really just an integer).

[Altera_Forum]

I figured out that the ADC gives a 12bit unsigend "straight binary" and I think that will be just an integer. For the streaming architecture I use for the FFT, I see it requires a "block floating point representation". That does not sound like a regular "straight binary" to me. 

 Should I convert it to a floating point binary?

[Altera_Forum]

--- Quote Start ---  For the streaming architecture I use for the FFT, I see it requires a "block floating point representation". That does not sound like a regular "straight binary" to me.  --- Quote End ---   I don't believe that you read the FFT MegaFunction users manual very thoroughly.   The nature of FFT transformation involves that the input and output data are complex numbers. They are represented by a pair of signed numbers (2s complement) for real and imaginary part. Because many physical signals, e.g. recorded sound are real only, the imaginary part of the input may be possibly zeroed.  The users manual also explain the block floating point concept. It means that a single exponent for the output data block is also generated during transformation. It's just an exponentional scaling factor that allows the FFT core to better utilize the numeric resolution. The output signal is still signed binary.  Straight binary will be converted to signed by inverting the MSB.

[Altera_Forum]

Hey guys, I need your help again. 

 I got it all worked out with downscaling my 50mhz clock to 32mhz and deviding that with 10 so I got a 3.2mhz clock for my ADC. The ADC works. But now I wanted to implement this little project that reads the ADC into a bigger project, which contains a PLL sopc component from the University Program of Altera.  While compiling, Quartus begins to whine about multiple PLL's are in the project that have te same startclock (the 50mhz clock). I now already tried to downscale the 27mhz clock to 16 and then devide that by 5 but no succes.  Please help

[Altera_Forum]

--- Quote Start ---  Hey guys, I need your help again.  I got it all worked out with downscaling my 50mhz clock to 32mhz and deviding that with 10 so I got a 3.2mhz clock for my ADC. The ADC works. But now I wanted to implement this little project that reads the ADC into a bigger project, which contains a PLL sopc component from the University Program of Altera.  While compiling, Quartus begins to whine about multiple PLL's are in the project that have te same startclock (the 50mhz clock). I now already tried to downscale the 27mhz clock to 16 and then devide that by 5 but no succes.  Please help  --- Quote End ---    looks like you already have PLL with 50MHz ref clk so all you need go to that PLL and add extra output clk at 32MHz instead of generating a separate PLL

[Altera_Forum]

--- Quote Start ---  looks like you already have PLL with 50MHz ref clk so all you need go to that PLL and add extra output clk at 32MHz instead of generating a separate PLL  --- Quote End ---    The bad thing is that it is a SOPC component that sets this PLL, which is a part of the Altera University program. How do I reach that?

[Altera_Forum]

--- Quote Start ---  The bad thing is that it is a SOPC component that sets this PLL, which is a part of the Altera University program. How do I reach that?  --- Quote End ---    That is when I am bad at... but if you manage to run the project to the end then open the hierarchy and click on PLL and hopefull megawizard will open it for your editing.  Or run megawizard and navigate to that PLL.

[Altera_Forum]

It does not open the wizard, it opens the SOPC builder:(. So there is also no PLL file to navigate to because it is all generated at the spot.

[Altera_Forum]

Let us wait for the tool gurus then.  

I have a project with SOPC components and can see them in the project hierarchy. You also tried 27MHz and couldn't get 16MHz then try 32MHz or 64 etc.

[Altera_Forum]

Here I post the component I customized. Maybe someone see's the error right away.  

 The thing I did is just copied the build instructions for the SDRAM en adjusted the name to ADC.

[Altera_Forum]

I got it fixed:)

[Altera_Forum]

Kaz and all the other people who helped me out, thank you very much! A few weeks ago I completed the project and completely passed the test at school. 

 Thanks again!