Error (10822)

[Altera_Forum]

Hello, please help me with this problem.  

 Code:  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity encoder is port( clk:in std_logic;  A:in std_logic;  B:in std_logic;  number:buffer unsigned(7 downto 0));   end encoder;   architecture main of encoder is --signal number: unsigned (7 downto 0):=(others=>'0'); begin --led<=number;     process(A,B) begin if falling_edge(A) then if B='0' then number<=number + 1;  end if; if B='1' then number<=number - 1 ; end if; end if; if rising_edge(A) then if B='0' then number<=number - 1;  end if; if B='1' then number<=number + 1 ; end if; end if;   end process; end main;  thanks

[Altera_Forum]

Would be more effective provide the exact line on which this error happened. 

The expected error log format on quartus2 for this ID is "hdl error at <location>: "

[Altera_Forum]

You are using both rising edge and falling edge in the same process. Don't do that. Synchronous designs are designed to run on one edge, typically rising edge. There are only certain specialized cases like DDR where both edges are to be used. Those situations are to simply clock in data, not implement some logic function as you are doing. 

 Kevin Jennings

[Altera_Forum]

--- Quote Start ---  You are using both rising edge and falling edge in the same process.  --- Quote End ---    Although being a bad style, is it supposed to be an error at all ? Just a guess, but would't be due to the fact that the code has cascaded "if...end if" implementations for the same variable ?  ... if B='0' then number<=number + 1; end if; if B='1' then number<=number - 1 ; ...

[Altera_Forum]

--- Quote Start ---  Although being a bad style, is it supposed to be an error at all ? Just a guess, but would't be due to the fact that the code has cascaded "if...end if" implementations for the same variable ?  ... if B='0' then number<=number + 1; end if; if B='1' then number<=number - 1 ; ...  --- Quote End ---    The error in the in the post titles - it appears the OP is trying to synthesise the design - which for and FPGA would be illegal with 2 edges.

[Altera_Forum]

--- Quote Start ---  Although being a bad style, is it supposed to be an error at all ?  --- Quote End ---  It would not be an error for a simulator, but it would be an error for some of today's (and all of yesterday's) synthesis tools. Tomorrow's synthesis tools might be quite happy implementing logic clocked by both edges...but we're not up to tomorrow yet.   --- Quote Start ---  Just a guess, but would't be due to the fact that the code has cascaded "if...end if" implementations for the same variable ?  --- Quote End ---  No, because that is not an error in simulation or synthesis. If that gets flagged as an error by some tool, you would submit a bug report to the tool supplier.  Kevin Jennings