Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

Error (14566): The Fitter cannot place 4 periphery component(s) due to conflicts with existing const

yy1
Beginner
599 Views

Hi,

How can fix the errors?

I really can't understand

 

Error (175001): The Fitter cannot place 1 HSSI_PMA_CDR_PLL, which is within Transceiver Native PHY Intel Arria 10 FPGA IP edp_rx_phy_16b_altera_xcvr_native_a10_181_gxzw7bi.
Info (14596): Information about the failing component(s):
Info (175028): The HSSI_PMA_CDR_PLL name(s): rx_phy_atop:i20_rx_phy_atop|IP_U40_COMBORXPHY_5P4G_03B_V007S1_dft_wrap:i10_IP_U40_COMBORXPHY_5P4G_03B_V007S1_dft_wrap|IP_U40_COMBORXPHY_5P4G_03B_V007S1:i_IP_U40_COMBORXPHY_5P4G_03B_V007S1|edp_rx_phy_top:i_edp_rx_phy_top|edp_rx_phy_16b:i_edp_rx_phy_16b|edp_rx_phy_16b_altera_xcvr_native_a10_181_gxzw7bi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_channel_pll.inst_twentynm_hssi_pma_channel_pll
Error (16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): Could not find path between the HSSI_PMA_CDR_PLL and destination HSSI_PMA_RX_DFE
Info (175027): Destination: HSSI_PMA_RX_DFE rx_phy_atop:i20_rx_phy_atop|IP_U40_COMBORXPHY_5P4G_03B_V007S1_dft_wrap:i10_IP_U40_COMBORXPHY_5P4G_03B_V007S1_dft_wrap|IP_U40_COMBORXPHY_5P4G_03B_V007S1:i_IP_U40_COMBORXPHY_5P4G_03B_V007S1|edp_rx_phy_top:i_edp_rx_phy_top|edp_rx_phy_16b:i_edp_rx_phy_16b|edp_rx_phy_16b_altera_xcvr_native_a10_181_gxzw7bi:xcvr_native_a10_0|twentynm_xcvr_native:g_xcvr_native_insts[3].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pma_rev_20nm5:inst_twentynm_pma|gen_twentynm_hssi_pma_rx_dfe.inst_twentynm_hssi_pma_rx_dfe
Error (175022): The HSSI_PMA_CDR_PLL could not be placed in any location to satisfy its connectivity requirements
Info (175021): The HSSI_PMA_RX_DFE was placed in location HSSIPMARXDFE_4H3
Info (175029): 71 locations affected
Info (175029): HSSIPMACDRPLL_1C0
Info (175029): HSSIPMACDRPLL_1C1
Info (175029): HSSIPMACDRPLL_1C2
Info (175029): HSSIPMACDRPLL_1C3
Info (175029): HSSIPMACDRPLL_1C4
Info (175029): HSSIPMACDRPLL_1C5
Info (175029): HSSIPMACDRPLL_1D0
Info (175029): HSSIPMACDRPLL_1D1
Info (175029): HSSIPMACDRPLL_1D2
Info (175029): HSSIPMACDRPLL_1D3
Info (175029): HSSIPMACDRPLL_1D4
Info (175029): HSSIPMACDRPLL_1D5
Info (175029): and 59 more locations not displayed

0 Kudos
10 Replies
Deshi_Intel
Moderator
576 Views

Hi,


Based on the fitter error report, likely there is an pin placement issue on either your CDR refclk pin or transceiver Rx channel pin


I can help to review your design if you can share your archived design QAR file here.


Thanks.


Regards,

dlim


yy1
Beginner
565 Views

Use tool : Quartus 18.1 prime standard

Family: Arria 10

Device: 10AX115S3F45E2SGE3

below is design (rx_cdr_refclk0 = 100MHz)

design_block_diagram.JPG

pin planner

set_location_assignment PIN_AC8 -to rx_cdr_refclk0
set_location_assignment PIN_AC7 -to "rx_cdr_refclk0(n)"
set_instance_assignment -name IO_STANDARD LVDS -to edp_ref_clk_p

set_location_assignment PIN_H5 -to rx_serial_data[0]
set_location_assignment PIN_G7 -to rx_serial_data[1]
set_location_assignment PIN_F5 -to rx_serial_data[2]
set_location_assignment PIN_E7 -to rx_serial_data[3]

set_location_assignment PIN_H6 -to "rx_serial_data[0](n)"
set_location_assignment PIN_G8 -to "rx_serial_data[1](n)"
set_location_assignment PIN_F6 -to "rx_serial_data[2](n)"
set_location_assignment PIN_E8 -to "rx_serial_data[3](n)"

set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[0]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[1]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[2]
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data[3]

yy1
Beginner
563 Views

Hi dlim,

If I try to modify design as below, the error message disappear,

but the source ref clk of the frequency of rx_clkout_16b and rx_clkout_20b  are different make 16_to_20bit_fifo module error.

modify_design_block_diagram.JPG

Therefore, I want to use the original design.

What's the problem of the original design?

yy1
Beginner
547 Views

Hi @Deshi_Intel ,

Do you have any idea ? 

Thanks for help.

Jamie

Deshi_Intel
Moderator
533 Views

Hi,


From the diagram that you drew, likely this is due to resource sharing issue.

  • You are using same CDR_refclk source to clock 2 NativePHY IP where by one transceiver bank only contains 6 channel.
  • If you are using CMU PLL, then it will eat up extra transceiver channel as well.
  • I am guessing once you remove the second NativePHY design then it free up some transceiver channel resource, that's why no more error


I can't analyze the issue further unless you can share with me your design QAR file. I need to cross check your NativePHY IP setting vs your transceiver pin setting.


Anyway, my suspect is due to insufficient transceiver channel resource sharing issue that caused the error


Thanks.


Regards,

dlim



yy1
Beginner
529 Views

Hi Dlim,

Thanks for your explain.

And what's the QAR file mean ? How can I get this file?

Thanks

Jamie

Deshi_Intel
Moderator
521 Views

HI,


Once you completed Quartus Analysis and Synthesis compilation, then you can goto

  1. In the Quartus II software, from the Project menu, choose Archive Project.
  2. Quartus will compress your Quartus design into *.qar file that you can share to me


You can refer to below link for more detail.


Let me know you are using which Quartus version


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
435 Views

HI,


Just to follow up.


Do you still plan to share your design for me to review ?


Thanks.


Regards,

dlim


yy1
Beginner
400 Views

Hi Dlim,

Sorry for replying late.

I have already change my design let project can keep going.

I will modify the design back to the original version then share design to you one day.

Thanks for your help.

Jamie 

Deshi_Intel
Moderator
403 Views

HI,


I am setting this case to closure since I never hear back from you.


Regards,

dlim


Reply