Error 17044 in nios design with sdram

[Altera_Forum]

Hi, 

 I have built a design using Nios core and sdram (dd3 sdram controller with UniPHY). I get the following error during compilation:  Error (17044): Illegal connection found on I/O input buffer primitive nios:inst|nios_sdram_new:sdram_new|nios_sdram_new_p0:p0|nios_sdram_new_p0_memphy:umemphy|nios_sdram_new_p0_new_io_pads:uio_pads|nios_sdram_new_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst|strobe_in. Source IO nios:inst|nios_sdram_new:sdram_new|nios_sdram_new_p0:p0|nios_sdram_new_p0_memphy:umemphy|nios_sdram_new_p0_new_io_pads:uio_pads|nios_sdram_new_p0_altdqdqs:dq_ddio[3].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer.  I am unable to understand why do I get this error?  Can anybody help me out?  Thanks.

[Altera_Forum]

Hello, 

 Carefully read last few words in error : "XXXX also drives out to other destination than the buffer." It suggests that one of your ports of sdram ( probably strobe_in ) has been connected to other logic besides to buffer. I think it should have connection only to buffer.  I hope this will help.  Cheers, Bhaumik

[Altera_Forum]

I dont think I have connected it wrongly. What are the correct connections to make? I just have two connections, the clock and reset. What connections are to be made for the sdram?

[Altera_Forum]

I read somewhere that running the pin_assignment.tcl script can sort this. But even this script is to run after a successful Analysis and Synthesis. But I cannot get past this error. 

Please help.

[Altera_Forum]

Hello, 

 Is it possible to upload your project here in archived form? I would like to have a look at it. To archive project, select archive project... under project Tab.  Cheers, Bhaumik