Quartus State Machine Viewer bug or fsm design error

[Altera_Forum]

Hello. 

I have a problem with synthesis fsm in quarus which the reason I think is Quartus bug. I have complicated design that compile in Quartus, Modelsim and it works in simulation (gate-level) but not on chip. I use Signal tap and catch somthing strange bug in one of design's fsm. I try to watch this fsm in Quartus State Machine Viewer but it doesn't display any bubble-diagram: if I click on the "Encoding" tab all the states are shown in the state table, but nothing in the "Transitions" section. Try to understand the reason why it doesn't show diagram I reduce my design to locate the problem and as a result I get simple moore fsm such as in Quartus template with little difference. Here the code(Verilog):   module test_moore #( parameter WIDTH = 7 ) ( input clk, reset, input [WIDTH-1:0]test_i, output reg [1:0] out );  // Declare state register reg [1:0]state;   // Declare states localparam S1 = 0, S2 = 1, S3 = 2;   // Output depends only on the state always @ (state) begin case (state) S1: out = 2'b11; S2: out = 2'b00; S3: out = 2'b10; default: out <= 2'b00; endcase end  reg [WIDTH-1:0]test_cnt; reg [WIDTH-1:0]test;  // Determine the next state always @ (posedge clk or posedge reset) begin if (reset) begin state <= S1; test <= {WIDTH{1'b0}}; test_cnt <= {WIDTH{1'b0}}; end else case (state) S1: begin test <= test_i; state <= S2; end S2: if (test_cnt == test) begin test_cnt <= {WIDTH{1'b0}}; state <= S3; end else begin test_cnt <= test_cnt+1'b1; state <= S2; end S3: state <= S1; endcase end   endmodule   If I synthesis this code in Quartus and I get something strange:   1) If I synthesis(in Quartus)/compile(in Modelsim) it with parameter WIDTH = 8 (and more) I get: in Quartus: - no warnings - In Quartus State Machine Viewer there is no bubble-diagram (Why?) in Modelsim: - recognized fsm and show bubble-diagram (It's OK). 2) If I synthesis(in Quartus)/compile(in Modelsim) it with parameter WIDTH = 7 (and less) I get: in Quartus: - no warnings - In Quartus State Machine Viewer show bubble-diagram (It's OK) in Modelsim: - recognized fsm and show bubble-diagram (It's OK).   This results the same for Quartus 13.1 Subscribe edition and Quartus 15.0 Web edition.   So I have following questios:  1) Why Quartus recognized fsm but does not show diagram in one case but Modelsim does? 2) If this fsm design is not correct, how fsm correctness may depend on counter width in this design?  3) If it is Quartus bug, which result I should trust about correctness of my fsm design for compilation flow in Quartus?   Thanks a lot!