Intel® Quartus® Prime Software
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Error (174068): Output buffer atom "soc_system:soc_inst|soc_system

Altera_Forum
Honored Contributor II
2,416 Views

Hi, 

 

I have built up an FPGA system in Qsys starting with the GHRD reference design and adding components. I actually built a simialr system for an Arria V Dev Board and that worked fine. Now when compileing in Quartus after a succesful generate in Qsys I get 100's of error messages like this one: 

 

Error (174068): Output buffer atom "soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination 

 

The rest of the errors are in the attached file joe.txt 

Any suggestions? 

 

Thanks Martin
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2 Replies
Altera_Forum
Honored Contributor II
1,130 Views

I'm seeing this same error. Any suggestions?

jagumiel
Novice
930 Views

I came here loooking for a solution, but I founded what I was doing wrong.

 

After the first compilation, when the fitter fails, you must run the following TCL scripts:

hps_sdram_p0_parameters.tcl

hps_sdram_p0_pin_assignments.tcl

JÁnge_0-1614602969674.png

 

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