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Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)



I am using Stratix10 1SD280PT2F55E2VGS1

And assign the refclk pin to:

set_location_assignment PIN_AT44 -to "pcie_refclk0(n)"
set_location_assignment PIN_AT45 -to pcie_refclk0
set_location_assignment PIN_AP44 -to "pcie_refclk1(n)"
set_location_assignment PIN_AP45 -to pcie_refclk1

But when fitting, I saw such error:

Error (175020): The Fitter cannot place logic pin in region (3, to (3, 9), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): pcie_refclk0
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected)
Info (175029): pin containing PIN_AT45
Info (175015): The I/O pad pcie_refclk0 is constrained to the location PIN_AT45 due to: User Location Constraints (PIN_AT45) File: Line: 244
Info (14709): The constrained I/O pad is contained within this pin
Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
Error (16297): An error has occurred while trying to initialize the plan stage.
Error: Quartus Prime Fitter was unsuccessful. 6 errors, 2 warnings

Do you have any ideas about this issue?

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2 Replies



I am sorry that you are facing this problem. I will try my best to help you. 

I believe these fitter errors are due to the invalid reconfiguration clock pin location assignments in the Intel Stratix 10 Hard IP for PCI Express MX H-Tile ES1 FPGA Devkit Design Example. Please go through this workaround:


Thank you. 





Is all of your questions addressed? I will close this case in 3 days if there is no response from you.