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Honored Contributor I
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Error (18994): configuration scheme "passive serial" is not valid for the device

I'm trying to synthesize a System Verilog RTL design to a Stratix 10 device using quartus II v.17 but keep getting the following error. Info (12627): Pin ~ALTERA_MSEL0~ is reserved at location AY8 

Info (12627): Pin ~ALTERA_MSEL1~ is reserved at location AY13 

Info (12627): Pin ~ALTERA_MSEL2~ is reserved at location AR14 

Error (18994): configuration scheme "passive serial" is not valid for the device 

 

 

All my top-level ports have been assigned VIRTUAL_PIN ON as this is just a small part of a larger design and I just want to see if it synthesizes. The error occurs for all Stratix 10 devices. The MSEL# pin locations vary per device. 

What is causing the error and how do I fix it? How do I tell Quartus II not to use "Passive Serial"? 

Thank you.
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Honored Contributor I
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Hi, 

 

go to Asigments-> Device -> Device and Pin options -> Configuration to change configuration mode.  

Also you can try to play with settings in Asigments-> Device -> Device and Pin options -> Dual-Purpose Pins section
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Honored Contributor I
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Thank you!! 

This fixed the problem. 

 

 

 

--- Quote Start ---  

Hi, 

 

go to Asigments-> Device -> Device and Pin options -> Configuration to change configuration mode.  

Also you can try to play with settings in Asigments-> Device -> Device and Pin options -> Dual-Purpose Pins section 

--- Quote End ---  

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