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Honored Contributor I
707 Views

Instantiating VHDL entities into a Verilog top level

I would like to instantiate some VHDL entities into A Verilog top level. 

Any ides on how to do this?
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Honored Contributor I
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You don't have to do anything special. Just map the ports in your Verilog instantiation as usual.

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Honored Contributor I
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Thanks, that did it.

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