Error: Can't synthesize current design -- Top partition does not contain any logic

[Altera_Forum]

Error: Can't synthesize current design -- Top partition does not contain any logic 

When I use megacore ip to generate the FFT in my design,however this error occourd .I used all ways that I konw,but still can not slove it.Can anyone to help me ?

[Altera_Forum]

Study the analysis and synthesis messages. Most likely you have lots of messages about logic getting removed. Start at these. There will also be sections of the report on removed nodes that triggered other things being removed. This is caused by having something necessary incorrectly tied off(like a clock or reset). This is somewhat strange to occur in your top-level, since you don't actually connect your top-level ports, they just go to pins. Most likely it's at a lower-leve hierarchy where a clock or something isnt' tied up, all that logic gets removed, and due to reductions, everything else gets removed. 

The other possibility is you have almost no messages, in which case you're reading in an empty file(it may have an entity and no architecture, or something like that).

[Altera_Forum]

Thanks a lot for your reply!  

I designed another bdf file,but this problem is still exesting.So I think that it must be some probems on my way of designing.But I will try again in your ways :) .

[Altera_Forum]

Are your sure if your bdf file is enabled as design top?

[Altera_Forum]

Yes ,I am sure. 

I asked my teacher,he saied he don't konw .So I did a expeiment that use the FFT core in a design and conect all the inputs and outputs,however it works OK.Then I think there must be some problem exeist in my previous design.Maybe it can not meet the timing requirements or others.

[Altera_Forum]

No, the problem can't be related to timing. It's typically a design without any relation of in and outputs.

[Altera_Forum]

The soution is simple. Just open the top level bdf file and right click on your block. Then click on the "generate pins for symbol ports". Recompile the project it is done. 

 After the compilation you can change the pin asssignments as you wish.

[Altera_Forum]

Thanks for all your help! Now the problem is solved.But all your advice is helpfull,though your suggestion I learned a lot about the sythesis , compilation and design skills.

[Altera_Forum]

All your answers ahout this problem are right.Any Information or pointers to literature would be welcome.