altlvds Transmitter in MegaWizard

Altera_Forum · ‎05-25-2008

Hi All,

I am currently using 'altlvds' for transmitting data(See Below).

For tx_in I have assigned a 10 bit data and for tx_inclock I assigned 100Mhz CoreClock.

I am not getting any data from the output ports.

Could anyone please help me in regard?

Thanks in advance

Regards

Sandeep

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY LvdsTx IS

PORT

(

tx_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

tx_inclock : IN STD_LOGIC := '0';

tx_coreclock : OUT STD_LOGIC ;

tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_outclock : OUT STD_LOGIC

);

END LvdsTx;

ARCHITECTURE SYN OF lvdstx IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC ;

SIGNAL sub_wire2 : STD_LOGIC ;

COMPONENT altlvds_tx

GENERIC (

common_rx_tx_pll : STRING;

deserialization_factor : NATURAL;

implement_in_les : STRING;

inclock_data_alignment : STRING;

inclock_period : NATURAL;

inclock_phase_shift : NATURAL;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

number_of_channels : NATURAL;

outclock_alignment : STRING;

outclock_divide_by : NATURAL;

outclock_phase_shift : NATURAL;

outclock_resource : STRING;

output_data_rate : NATURAL;

registered_input : STRING

);

PORT (

tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_outclock : OUT STD_LOGIC ;

tx_coreclock : OUT STD_LOGIC ;

tx_in : IN STD_LOGIC_VECTOR (9 DOWNTO 0);

tx_inclock : IN STD_LOGIC

);

END COMPONENT;

BEGIN

tx_out <= sub_wire0(0 DOWNTO 0);

tx_outclock <= sub_wire1;

tx_coreclock <= sub_wire2;

altlvds_tx_component : altlvds_tx

GENERIC MAP (

common_rx_tx_pll => "ON",

deserialization_factor => 10,

implement_in_les => "OFF",

inclock_data_alignment => "UNUSED",

inclock_period => 10000,

inclock_phase_shift => 0,

intended_device_family => "Stratix",

lpm_hint => "CBX_MODULE_PREFIX=LvdsTx",

lpm_type => "altlvds_tx",

number_of_channels => 1,

outclock_alignment => "UNUSED",

outclock_divide_by => 10,

outclock_phase_shift => 0,

outclock_resource => "AUTO",

output_data_rate => 1000,

registered_input => "TX_CORECLK"

)

PORT MAP (

tx_in => tx_in,

tx_inclock => tx_inclock,

tx_out => sub_wire0,

tx_outclock => sub_wire1,

tx_coreclock => sub_wire2

);

END SYN;

Altera_Forum · ‎05-25-2008

From the parameter list, I read Stratix device and data rate of 1000 MHz. I thought maximum datarate for Stratix LVDS transmitter would be 840 MHz?

Altera_Forum · ‎05-26-2008

I am glad to receive a quick response from you.

Ya you are right its 840MHz. But in my design I have used 'output data rate' is 1000Mbps and a deserilization factor of 10 hence the input clock frequency is 100Mhz and out clock frequency is 1Ghz (which is not possibe as it is limitted to a maximum of 717 Mhz). Therefore I have used a outclock divide factor of 10.

The issue is resolved ;). The problem was when I tried to simulate my project in Modelsim the Stratix PLL was not getting locked with the incoming clock. A friend of mine suggested me to change time to 1ps before simulation. Now, the Stratix PLL is locked to the incoming clock and it is working fine.

Thanku very much

reg

Sandeep

Altera_Forum · ‎05-26-2008

Yes, I also took some time before I realized how to operate PLLs in ModelSim. By the way, you should always mention if it's a simulation or hardware problem. The comfortable thing in ModelSim is, you can inspect any signal, e. g. PLL locked signal without recompiling the design. So it's basically easy to identify a non-operating PLL.

Altera_Forum · ‎05-26-2008

Ohh.. I am sorry for not mentioning it. Ya! ur right I actually dint notice the warning message.

Danke,

Sandeep