Error Code: 8 for command

Altera_Forum · ‎07-18-2011

Hello,

I'm trying to burn the example "count binary" code into CFI flash on the cyclone III starter board.

I'm getting the error,

"Error code: 8 for command: nios2eds/bin/nios2-flash-programmer "C:/Users/dsmith/Desktop/Projects/Incremental_FPGA/incFPGA_EPCS_Board/flash/incFPGA_EPCS_Board_Prog_cfi_flash_0.flash" --base=0x0 --sidp=0x1011038 --id=0x0 --timestamp=1311008727 --device=1 --instance=0 '--cable=USB-Blaster on localhost [USB-0]' --program "

Here is my procedure in some detail.

I created the Qsys system ( see image "Qsys" )

I generated that system, and placed it in the bdf.

I programmed the flash in Quartus II using this quide (http://www.altera.com/literature/ug/ug_ciii_starter_kit.pdf)

I then attempted to program the CFI in NIOS II using the provided "count binary" code and got the error above. You can see a screen shot in the file "NIOSIIProg" below.

Thanks for your help.

alphaOri

Altera_Forum · ‎07-19-2011

I take it that this board has flash and a CPLD rather than an EPC configuration device. I have one of the old Stratix 1S80 DSP boards and am stuck in this boat. I don't know whether it is a matter of pin assignment, pin type, memory timing parameters, or what. I get the same "Error code: 8..." message.

Altera_Forum · ‎07-26-2011

I've got the parallel flash working now (the 128P30 on the Cyclone III starter board). I worked it out with Altera support (thanx guys).

In qsys. Make sure you include a Tri-State Conduit Bridge and a Generic Tri-State Controller. In the Generic Tri-State Controller you'll be able to select which flash you are using. Those two were all I needed for interfacing with the flash. (see attached image)

Make sure you set the 0th line from the address bus from nios II to xxxP30 flash to be virtual. You can do this by ignoring that pin in the pin planner and adding this line to your .bsf file:

set_instance_assignment -name VIRTUAL_PIN ON -to <your_address_bus>[0]

If you are using the 128P30, qsys will give you a 24 pin bus <your_address_bus>[23..0]. So we use <your_address_bus>[0] for virtual then use <your_address_bus>[23..1] to connect to the first 23 lines of your CFI flash (1-23). (For the 256P30, you only connect 24 pins, and for the 512P30, you connect all 25 pins). See attached image.

For programming FPGA configuration, follow the directions in the appendix of Cyclone III FPGA Starter Kit User Guide. For programming software, just open nios II flash programmer, add new, point to .socpinfo file for nios II qsys design, add the .elf file, and click program.

Disclaimer: I'm a beginner so there may be problems in the above method although it worked on my setup.

Altera_Forum · ‎07-26-2011

Thank you thank you thank you. I'll attempt to use this info to get my Stratix DSP dev kit flash working sometime in the next couple of weeks. I know that there are still some people out there with these Stratix I and II boards. If it works, I'll post my solution here.

Altera_Forum · ‎02-10-2012

I struggled with this same "error 8" for several days on my custom design before our Altera rep helped me through it. I'm using the Intel 256P30 with an EP3C40 FPGA in an active parallel setup, so no configuration device, just flash and JTAG.

Selecting the tri state controller with 256P30 preset didn't work for me. I had to select the older CFI component with the 256P30 setup, then hook it up to an avalon master bridge and hook both up to clk, rst, etc. As Qsys suggested, I then ran the SOPC->Qsys conversion.

I set the address[0] line as virtual in the assignment editor.

In my VHDL I am manually driving the leftover flash lines needed for AP configuration like this:

    flash_adv_n        <=    '0';
    flash_clk        <= '0';
    flash_rst_n        <= '1';
    flash_wp        <= '1';
    flash_wait       <= '0';

Have not yet seen if the AP configuration will work yet, but I am able to program the flash at least with this setup.

Altera_Forum · ‎02-17-2012

Hi All,

Thanks for all the info concerning the flash. I see this is an old thread so I don't know if anyone will see this but it seems like the best place for it.

I have a stratix III dev kit, and I was wondering if anyone has had success building a qsys system for this board. The flash part on the board is the 512P30 part. I've followed instructions posted earlier, but so far haven't had any luck. I've tried both the generic tristate controller, and the older CFI component which then is upgraded though the SOPC to QSYS upgrade. Any ideas?

Thanks so much for your help.

Altera_Forum · ‎03-21-2014

Hi All,

I have the same problem, but in a little bit different situation. I am using DE2 board with Cyclone II FPGA. The university program SoPC extension supports the flash controller IP core. I have built my design and the flash programmer started to work but finally it stopped with the same error. Could you help in that case? Address[0] virtual assignment did not help. I have attached pictures about the system.

Thanks&Regards,

Zsolt