Error ID 18694: Still not resolved ???

[JohnGermany]

I have a LVDS SERDES TX IP in bank 2J of a Cyclone 10 GX device.

I have a shared clock input pin in bank 3B.

The current Cyclone 10 GX Core Fabric and IO manual, section 5.6.6.3, states that this clock pin on bank 3B could be used as reference clock for the bank 2J SERDES TX IOPLL, when promoted. I did promote that clock to GLOBAL.

I get error message ID 18694, which states that this connection is forbidden to be used.

This problem has been discussed here over several years. Could it be true that there still is no other solution to that problem than to revert to QPP 18.0 ??? If so, I find that rather ridiculous, since I am very satisfied with rather low clock rates, just a very few hundred MHz, so there is no concern about jitter. After all, that reference clock for a TX SERDES has to come from somewhere, and I could have a large number of TX SERDES within my design. So some shared clock clearly is reasonably required.

Any workaround is highly appreciated.

Thanks and best regards

John

P.S. I read that there does exist some secret, magic escape to that. In view of the clear unsuitability of blocking that route, please let me have that code.

[FvM]

Hi John,
I wasn't aware of paragraph 5.6.6.3. The relation of 5.6.6.2.2 "The reference clock to the I/O PLL for the DPA or non-DPA LVDS receiver must come from the dedicated reference clock pin within the I/O bank" and 5.6.6.3 (you can manually promote reference clock from other I/O bank) is however not clearly stated. The manual can be read so that 5.6.6.3 doesn't apply for receiver SERDES.

I checked that manual promotion doesn't work for receiver PLL in Quartus Pro 22.4 and 24.3. You need to use an undocumented quartus.ini entry to enable reference clock promotion from other I/O bank.

I understand that Intel/Altera disabled reference clock promotion after Quartus 18 to "save" Cyclone 10 GX clock performance specification. However, as you stated, there are many medium speed SERDES designs that can well work with promoted reference clock.

Thus we are still waiting for an Altera application note undisclosing the respective Quartus.ini options. In the meantime, you may get on your FAE's nerves asking for the information.

Regards

Frank

[JohnGermany]

Hi Frank,

thanks for your note. So it appears that we are on one line.

We did forward the question to our FAE engineer here, still waiting for the reply.

Meanwhile, I found a workaround:

- I need to transform the global clock from bank 3B into a local clock for bank 2J

- I define a bidirectional LVCMOS IO buffer on one of the bank 2J dedicated clock pins, otherwise unused

- I route the global clock to the input of that bidir buffer

- I retrieve the local bank 2J clock from the output of that bidir buffer

- of course I need OE=1, but Quartus forbids that as a static assignment (!!!!)

- so I create some Mickey-Mouse logic which toggles OE at some irrelevant point in time

- works beautifully, even at 1360 Mbit/sec, 136 MHz clock at factor 10 SERDES. I do not need that high rates, but testing it out just for fun.

Best regards

John

[FvM · Accepted solution]

Hi,
hard to believe that you need to refer to weird workarounds like this...

Check your private message folder.

Regards,
Frank