Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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IDENTIFYING THE ECC BYTE IN 40 bit DATA BUS OF EMIF CONTROLLER of ARRIA 10 HPS

MHada
Principiante
742 Visualizações

Dear All,

 

Designing ARRIA 10 board with 32 bit DDR4 interface (2 components - 4Gb each (256 X 16)) and the third component used for ECC - total 40 bit on the HPS side.

 

I am unable to identify the ECC byte of the 40 bit databus of DDR4 EMIF controller  on the HPS Side of ARRIA 10 from teh Quartus project. This may sound naïve but I am in that problem.

 

Although we are aware that lane 3 of 2K bank will be the ECC Byte for 32 bit DDR interface with 8 bit ECC but we are unable to understand teh same from pin files or RTL implementation.

 

The reason for such query is that till date we used lower byte of 3rd DDR chip as ECC on our hardware and the controller side also as DQ(32:39) data width. But now in ARRIA 10 N3F40 SX, PCB routing is such that DQ(0:7) looks to be a better choice for ECC which is connected to lower byte of 1st DDR chip and is mapped to 3rd lane of 2K bank. Quartus accepts this formation but I want to confirm the same from Quartus that lowest byte of DQ bus is ECC DQ(0:7) and the remaining 32 bit is data (DQ(8:39)) . Quartus project assigns DQ(0:7) to 2K bank lane 3 but how do we know that it is actually ECC byte from project, RTL or otherwise....

Can some please help us understand the same ....

 

 

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AdzimZM_Intel
Funcionário
686 Visualizações

Hi MHada,


DQ0 - DQ31 is Data pin, DQ32 - DQ39 is ECC pin.

The ECC pin should be placed in Lane 3 of IO Bank 2K as mentioned in the User Guide.

You can swap the pin placement in the Quartus and place the DQ32 - DQ39 in Bank 2K.


Regards,

Adzim



MHada
Principiante
450 Visualizações

Hi Adzim,

 

Thanks for the prompt reply.

 

Very sorry it got missed !! I am still under confusion on this.

 

When you talk about DQ0 - DQ31, are you talking about the controller signal name on Quartus or the data bus assigned on my schematic.

 

I find the DQ0 to DQ7 assigned to lane 3 in bank 2K and the project getting compiled in 32 bit data + ECC DDR4 configuration !!

 

Quartus should not compile the project if that is the case. I seriously think I am doing something wrong here !!

 

I will follow this closely. 

MHada
Principiante
448 Visualizações

Hi,  @AdzimZM_Intel 

 

I forgot to tell that I have attached my schematic and pin config files in previous post.

 

Pls help us in this !!

 

 

AdzimZM_Intel
Funcionário
589 Visualizações

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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