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Error Loading Design in Modelsim

Altera_Forum
Honored Contributor II
‎06-08-2010 07:26 AM
1,682 Views

I obtain the above error when trying simulate a design. 

# Loading work.Valid_Signal# Error loading design# Error: Error loading design # Pausing macro execution # MACRO ./DigitalAudioOutput_run_msim_rtl_verilog.do PAUSED at line 20 

 

line 20: vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L cycloneiii_ver -L rtl_work -L work -voptargs="+acc" DigitalAudioOutput_tb_08Jun2010 

 

No indicator what is the error abt. Any idea?
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