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Error:Port "cg" does not exist in macro function "ADD0"

Altera_Forum
Honored Contributor II
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So i got 8 error while compiling this 4 bit Carry-lookahead adder. I got the above error for ports cg and cp in macro functions ADD0-ADD3. For my code check the attachments. Edit: Here i've copied the code in: 

 

 

--- Quote Start ---  

 

library IEEE; 

use IEEE.std_logic_1164.all; 

entity cla4 is -- 4-bit CLA structural model: top entity 

port( a, b: in std_logic_vector(3 downto 0); 

carryin: in std_logic; 

sum, ch, cq: out std_logic_vector(3 downto 0); 

cgout, cpout, overflow: out std_logic); 

end cla4; 

architecture arch of cla4 is 

component fagp -- component declaration 

port( a, b, cin: in std_logic; 

sum, cg, cp: out std_logic); 

end component; 

component cla_logic -- component declaration CLA-generator 

port( g, p: in std_logic_vector(3 downto 0); 

cin: in std_logic; 

c: out std_logic_vector(2 downto 0); 

cgout, cpout: out std_logic); 

end component; 

signal carry: std_logic_vector(3 downto 0); --local signals 

signal cg, cp: std_logic_vector(3 downto 0); 

signal cout: std_logic; 

begin 

carry(0) <= carryin; 

ADD0: 

fagp 

port map (a(0), b(0), carry(0), sum(0), cg(0), cp(0)); 

ADD1: 

fagp 

port map (a(1), b(1), carry(1), sum(1), cg(1), cp(1)); 

ADD2: 

fagp 

port map (a(2), b(2), carry(2), sum(2), cg(2), cp(2)); 

ADD3: 

fagp 

port map (a(3), b(3), carry(3), sum(3), cg(3), cp(3)); 

--generate carries from 

--propagate and generate values 

--from full_adder_g_p_g_p 

CLA: 

cla_logic 

port map(cg, cp, carryin, carry(3 downto 1), cout, cpout); 

cgout <= cout; 

overflow <= carry(3) xor cout; 

end arch; 

 

 

 

--- Quote End ---  

 

 

 

--- Quote Start ---  

 

library IEEE; 

use IEEE.std_logic_1164.all; 

entity cla_logic is 

port( 

G, P: in std_logic_vector(3 downto 0); 

CIN: in std_logic; 

C: out std_logic_vector(2 downto 0); -- “internal” carry 

CGOUT, CPOUT: out std_logic); 

end cla_logic; 

architecture arch of cla_logic is 

begin 

C(0) <= G(0) or (P(0) and CIN); 

C(1) <= G(1) or (G(0) and P(1)) or (CIN and P(0) and P(1));  

C(2) <= G(2) or (G(1) and P(2)) or (G(0) and P(1) and P(2)) or (CIN and P(0) and P(1) and P(2)); 

CGOUT<= G(3) or (G(2) and P(3)) or (G(0) and P(2) and P(3)) or (G(0) and P(1) and P(2) and P(3)) or (CIN and P(0) and P(1) and P(2) and P(3)); 

CPOUT<= (P(3) and P(2) and P(1) and P(0)); 

end arch; 

 

--- Quote End ---  

 

 

 

--- Quote Start ---  

 

library IEEE; 

use IEEE.std_logic_1164.all; 

entity fagp is 

port( a, b, cin: in std_logic; 

sum, g, p: out std_logic); 

end fagp; 

architecture arch of fagp is 

begin 

sum <= a xor b xor cin; 

p <= a and b; --complete this 

g <= a or b; --complete this 

end arch; 

 

--- Quote End ---  

 

 

 

Any Ideas??
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