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Altera_Forum
Honored Contributor I
1,535 Views

Error generating simulation files for Qsys system

I have a design using Cyclone IV, Quartus 17.0 

 

I have a Qsys system that includes a NIOS, DRAM controller, several standard peripherals, and then several IP blocks of my own design. 

 

I can generate the synthesis files fine, and the synthesis and place & route work as expected. 

 

But when I click the box to enable generating the simulation files I get this error: 

 

Error: DMA_SPI_0: DMA_SPI does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis. 

 

The DMA_SPI block is one of my blocks that I have instantiated in the Qsys design. It contains only Verilog RTL, there are no other modules instantiated in it. So this seems to be telling me that I can't use the Quartus tools to generate the simulation files when I have custom IP blocks.  

 

Is there a way to work around this? 

 

Rod
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2 Replies
Altera_Forum
Honored Contributor I
240 Views

Assuming you created this with the Component Editor, did you specify simulation file(s) on the Files tab? If you don't specify separate sim files (or choose to use the same files for synthesis and sim), you'll get this error.

Altera_Forum
Honored Contributor I
240 Views

Hi, 

 

Can you put your design.qar here so that we can have a look into it? 

 

Thanks, 

Best regards, 

Kentan 

(This message was posted on behalf of Intel Corporation)
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