Error in gate-level timing simulation using modelsim

[Altera_Forum]

When the design is synthesized and the FPGA target is either CYCLONE or CYCLONEII, the gate-level timing simulation operates properly. But, when the same design is synthesized and the target FPGA is CYCLONEIII, the gate-level timing simulation doesn't work properly. 

Is there a reason for this ? Thanks :)

[Altera_Forum]

--- Quote Start ---  When the design is synthesized and the FPGA target is either CYCLONE or CYCLONEII, the gate-level timing simulation operates properly. But, when the same design is synthesized and the target FPGA is CYCLONEIII, the gate-level timing simulation doesn't work properly. Is there a reason for this ? Thanks :)  --- Quote End ---     The testbench does not set up the inputs to meet the timing requirements.   Kevin Jennings

[Altera_Forum]

I'm sure that the testbench set up the to meet the timing requirements. 

If the timing requirements aren't met, the simulation should fail at any target FPGA, but it succeeded when the target FPGA is CYCLONE or CYCLONEII and fails when the target FPGA is CYCLONEIII.

[Altera_Forum]

Could you define "fails"... What do you get and what do you expect? Without this information it is hard to try and figure out what could be the problem. 

But I would bet on a timing problem too. Is the design properly constrained and does Timequest report any timing violation?

[Altera_Forum]

--- Quote Start ---  I'm sure that the testbench set up the to meet the timing requirements.  --- Quote End ---   You can only say that if you've verified that the signals are generated from the testbench at a time compatible with what the timing report for that design states.     --- Quote Start ---  If the timing requirements aren't met, the simulation should fail at any target FPGA,  --- Quote End ---   There is no basis for that statement. It is simply not true.   --- Quote Start ---  but it succeeded when the target FPGA is CYCLONE or CYCLONEII and fails when the target FPGA is CYCLONEIII.  --- Quote End ---   That just says that the system to debug is the one with the Cyclone III in it.   You still need to verify that the setup time requirements being reported by Quartus for the Cyclone III design are being met by your testbench.   The next step is to verify that the outputs being sampled by your testbench (assuming that you're doing this) are being collected at times compatible with the clock to output delays being reported by Quartus for the Cyclone III design.   Until you've done this, there isn't much for anyone to help you with. If you have done this, then opening a case with Altera would likely be in order as well.   Kevin Jennings

[Altera_Forum]

I mean by "fail" that the outputs of the design aren't true. Also, i re-checked the TimeQuest timing analysis report and no timing violations were found.

[Altera_Forum]

I synthesized the design at three different FPGAs(CYCLONE,CYCLONEII,CYCLONEIII), and i used the same testbench for the three cases. On Modelsim, in case of CYCLONE, pre-compiled simulation library of CYCLONE was required, in case of CYCLONEII, pre-compiled simulation library of CYCLONEII was required, and in case of CYCLONEIII, two pre-compiled simulation libraries were required (CYCLONEIII,ALTERA). For each case, i used the .vho and .sdo file of it. The results of the simulation are as expected in case of CYCLONE and CYCLONEII, but in case of CYCLONEIII it wasn't true. The timing analysis report has no timing violations. Is there extra configuration for ModelSim in case of CYCLONEIII ?

[Altera_Forum]

--- Quote Start ---  I mean by "fail" that the outputs of the design aren't true.  --- Quote End ---  this doesn't really help...   --- Quote Start ---  On Modelsim, in case of CYCLONE, pre-compiled simulation library of CYCLONE was required, in case of CYCLONEII, pre-compiled simulation library of CYCLONEII was required, and in case of CYCLONEIII, two pre-compiled simulation libraries were required (CYCLONEIII,ALTERA). For each case, i used the .vho and .sdo file of it.  --- Quote End ---  Do you have different warnings from Modelsim before it starts the simulation, when running for the Cyclone III? Warnings such as "Warning: No default binding for component: xxx" can meen it didn't find the correct component to instantiate from the libraries it has, and it will most probably give wrong simulation results.