Error message when simulating - "delay annotation information"

[Altera_Forum]

I get the following error message when I try to simulate anything with Quartus: 

Error: Can't continue simulation because delay annotation information for design is missing  I did edit "delay requirements" (under "assignments" -> "timing settings" ) after the error, and still get the same error. Is there anywhere else I can put this information in? Any ideas what I am missing?  I have 3 different "programs" / assignments that I am getting this same error message on.  Thanks for any advice!

[Altera_Forum]

--- Quote Start ---  I get the following error message when I try to simulate anything with Quartus: Error: Can't continue simulation because delay annotation information for design is missing  I did edit "delay requirements" (under "assignments" -> "timing settings" ) after the error, and still get the same error. Is there anywhere else I can put this information in? Any ideas what I am missing?  I have 3 different "programs" / assignments that I am getting this same error message on.  Thanks for any advice!  --- Quote End ---    Hi,  you have to run all processing step incl. the timing analysis. The missing delay information is extracted by the timing analyzer.  Kind regards  GPK

[Altera_Forum]

Ah-ha, thanks! I was not doing that.  

 So - another question - try to run the timing analysis, and get this: Error: Can't run Timing Analyzer (quartus_tan) -- Fitter (quartus_fit) failed or was not run   What/where is the "fitter?" ??? Thanks again!

[Altera_Forum]

--- Quote Start ---  Ah-ha, thanks! I was not doing that.    So - another question - try to run the timing analysis, and get this: Error: Can't run Timing Analyzer (quartus_tan) -- Fitter (quartus_fit) failed or was not run   What/where is the "fitter?" ??? Thanks again!  --- Quote End ---    Hi,  sorry my fault.  In order to run the timing analyzer you have to perform a complete run, which includes:  1. Analysis & Elaboration  Your HDL is analyzed , the Hierachy is extratcted etc..... 2. Synthesis  Your design is converted in Logic, Register .... 3. Mapping  Your design is mapped to FPGA resource like LUT's, DSP Blocks .... 4. Fitter  Your design is placed and routed  5. Timing Analysis  After Place&Route you can analysis the real timing of your design  That all you need to put your design in the FPGA.  Kind regards  GPK