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Error message

Altera_Forum
Honored Contributor II
1,303 Views

I do not understand why I am getting the error message for the code below.... 

 

Error (10818): Netlist error at up_dwn_counter.vhd(61): can't infer register for d_o[0] because it does not hold its value outside the clock edge 

 

Thank you in advance!! 

 

Bojan 

 

************************* 

 

library ieee; 

 

use ieee.std_logic_1164.all; 

--use ieee.numeric_std.all; 

use ieee.std_logic_arith.all; 

use ieee.std_logic_unsigned.all; 

 

 

 

 

entity up_dwn_counter is 

port ( 

 

rst : in bit; 

clk : in bit; 

--uartclk : out bit; 

u_d, cl :in bit; 

d_o : out std_logic_vector (31 downto 0) 

); 

end up_dwn_counter; 

 

 

 

 

architecture counter of up_dwn_counter is 

 

shared variable counter: std_logic_vector (31 downto 0);-- :="00000000000000000000000000000000";  

 

begin  

 

count: process (cl, rst, u_d)  

begin 

 

if (rst'event and rst = '1') -- This is supposed to check for rising edge of rst 

then  

d_o <= "00000000000000000000000000000000"; 

counter:="00000000000000000000000000000000"; 

 

 

if (cl'event and cl = '1') -- This is supposed to check for rising edge of cl 

then 

if (u_d = '1')  

then counter := counter + "1"; 

else counter := counter - "1"; 

end if;  

 

else 

 

if (cl'event and cl = '0')-- This is supposed to check for falling edge of cl 

then 

if (u_d = '0')  

then counter := counter - '1'; 

else counter := counter + '1'; 

end if;  

 

end if; 

 

d_o <= counter; -- to_StdLogicVector(counter);-- (31 downto 0); 

 

end if; -- clockevent 

end if; -- rst_event 

 

end process; 

 

end; -- end of architecture "counter"
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Altera_Forum
Honored Contributor II
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You need to think about what hardware you want to generate. A register is only sensitive to 1 clock edge, either rising or falling so if you remove the section of code that checks for the falling edge of cl then you should be ok.

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Altera_Forum
Honored Contributor II
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Always use the recommended coding style. See http://www.alteraforum.com/forum/showthread.php?p=3369#post3369 for a reference to the coding guidelines in the Quartus handbook.

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Altera_Forum
Honored Contributor II
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Thanks guys, I will have a look at recommendations...

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