Error msg when running the modelsim simulation on Quartus II

[Altera_Forum]

Hi all  

 Do you know how to solve this error?  refer attach  error:  >> Warning: can't rename "project_close_renamed": command doesn't exist Device family: Cyclone V Running quartus eda_testbench >> quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog four_bit_shift_reg_with_memory -c four_bit_shift_reg_with_memory_top {--vector_source=E:/FPGA_program/four_bit_shift_reg_with_memory_v2/test_ram.vwf} {--testbench_file=./simulation/qsim/four_bit_shift_reg_with_memory.vt} PID = 5748 ******************************************************************* Running Quartus II 32-bit EDA Netlist Writer  Version 13.0.0 Build 156 04/24/2013 SJ Web Edition  Processing started: Fri Jun 28 15:34:07 2013 Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog four_bit_shift_reg_with_memory -c four_bit_shift_reg_with_memory_top --vector_source=E:/FPGA_program/four_bit_shift_reg_with_memory_v2/test_ram.vwf --testbench_file=./simulation/qsim/four_bit_shift_reg_with_memory.vt Generated Verilog Test Bench File ./simulation/qsim/four_bit_shift_reg_with_memory.vt for simulation Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings  Peak virtual memory: 354 megabytes  Processing ended: Fri Jun 28 15:34:09 2013  Elapsed time: 00:00:02  Total CPU time (on all processors): 00:00:02 Running quartus eda_func_netlist >> quartus_eda --functional=on --simulation --tool=modelsim_oem --format=verilog four_bit_shift_reg_with_memory -c four_bit_shift_reg_with_memory_top  PID = 2248 ******************************************************************* Running Quartus II 32-bit EDA Netlist Writer  Version 13.0.0 Build 156 04/24/2013 SJ Web Edition  Processing started: Fri Jun 28 15:34:09 2013 Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog four_bit_shift_reg_with_memory -c four_bit_shift_reg_with_memory_top Generated file four_bit_shift_reg_with_memory_top.vo in folder "E:/FPGA_program/four_bit_shift_reg_with_memory_v2/simulation/modelsim/" for EDA simulation tool Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings  Peak virtual memory: 357 megabytes  Processing ended: Fri Jun 28 15:34:11 2013  Elapsed time: 00:00:02  Total CPU time (on all processors): 00:00:02 ******************************************************************* Running quartus modelsim >> vsim -c -do four_bit_shift_reg_with_memory.do PID = 3124  Reading C:/altera/13.0/modelsim_ase/tcl/vsim/pref.tcl     # 10.1d    # do four_bit_shift_reg_with_memory.do   # ** Warning: (vlib-34) Library already exists at "work".  #   # Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012  # ** Error: (vlog-7) Failed to open design unit file "four_bit_shift_reg_with_memory_top.vo" in read mode.  #   # No such file or directory. (errno = ENOENT)  # ** Error: c:/altera/13.0/modelsim_ase/win32aloem/vlog failed.  # Executing ONERROR command at macro ./four_bit_shift_reg_with_memory.do line 3

[Altera_Forum]

Have you tried running this using Nativelink? That might help you identify what the problem is