Error:"Connected system ID hash not found on target at expected base address"

[vietvu1912]

Hi, I try to run C file in FPGA Nios II and I receive a following error message: "Connected system ID hash not found on target at expected base address".

My .qsys had System ID peripheral IPcore.

My project with this qsys is attached under post.

Thanks a lot,

Viet

[BoonBengT_Intel]

Hi @vietvu1912,

Thank you for posting in Intel community forum and hope all is well.
Mind if I ask did you managed to programmed the correct sof successfully? Which quartus version and board are you using?

Would suggest on the following, check on the system.h files in BPS project to ensure system ID peripheral are listed with correct value, followed by regenerating the BSP to see if that helps.
As running the program in hardware, try to refresh the connection under 'Target Connections' tab.

You may also try checking 'Ignore mismatched system ID & timestamp' fields and run to the program to see if that helps.
Hope to hear form you soon.

Best Wishes
BB

[vietvu1912]

Hello, thanks for your reply.

I created a file that is identical to the qsys file of the project I downloaded from Intel and only removed the IPcore Triple speed Ethernet I don't use. I don't know if my .qsys is missing anything from that project, but every connection and IPcore I have installed is the same.

i use quartus pro 18.0 and my board is Cyclone 10Gx development kit.

can you tell me what is the peripherial ID representation value in system.h?

I also try checking 'Ignore mismatched system ID & timestamp' but .elf file download failed. I have refreshed the connection but Connected System ID and Connected system timestamp are still not found.

Can you support for me to solve this?

A project I downloaded from Intel and the system ID properties notification image is attached below:

[BoonBengT_Intel]

Hi @vietvu1912,

Apologies for the delay, if i understand correct you have downloaded the sample design from intel and removed the TSE IP, and are having issues in running in Nios.
If the IP are removed from the platform design, would suggest to check also on the quartus rtl part and remove the relevant section, and that should work after recompiling and program the board with the sof.

Just to ensure that the design example downloaded are not corrupted, would also suggest to build and compile without changes and running it in nios.
Please do let us know if that helps to clarify.

Best Wishes
BB

[BoonBengT_Intel]

Hi @vietvu1912,

Greetings, unfortunately as we do not receive any further clarification on what is provided. Hence we will no longer monitor this thread. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes
BB