Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15544 Discussions

Error related to defparam in Qsys system containing Nios

gyuunyuu
New Contributor II
520 Views

​I am trying to simulate a Qsys system containing Nios II and custom Qsys peripherals. I am using Quartus 18.0 and ActiveHDL 10.5a. The error that shows up at start of simulation is:

 

# ELAB2: Fatal Error: ELAB2_0093 The defparam statement from module "SPRINT_SYS_NiosII_cpu_register_bank_a_module" in "/T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a" points to variable "address_reg_b" in a non-Verilog design region "/T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a/the_altsyncram". # ELAB2: Last instance before error: /T_NIOS_TB/WRAPPER/u0/niosii/cpu/SPRINT_SYS_NiosII_cpu_register_bank_a # KERNEL: Error: E8005 : Kernel process initialization failed. # VSIM: Error: Simulation initialization failed.

 

It is not clear what this actually means. The SPRINT_SYS is the name of the Qsys system.

0 Kudos
2 Replies
gyuunyuu
New Contributor II
163 Views

​It seems that this error occurs because VHDL version of altsyncram is being instantiated in Verilog code of the Nios and passing defparam to generic does not seem to be working correctly.

The altsyncram is defined inside two places altera_mf.v and altera_mf.vhdl. My testbench compiles the VHDL variant. If I compile the Verilog variant then this error goes away.

Kenny_Tan
Moderator
163 Views
Good to hear that, some of the IP need to use verilog code. The VHDL variant is not supported for some IP
Reply