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MMorr23
Beginner
426 Views

PCIe IP example error: Failed to open design unit file "../../../top_core.vo" in read mode.

Hello, I cannot simulate the PCIe example from this PCIe doc "IP Compiler for PCI Express User Manual": https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

 

When I try to run the runtb.do script in Modelsim (To compile the testbench example), I get the error Failed to open design unit file "../../../top_core.vo" in read mode.

 

That file seems to not have been created on my computer... I don't know where it is supposed to come from.

 

 

I have purchased this Cyclone IV GX board with PCIe and cannot get any of the intel IP to simulate or build and run on this thing...

 

I am using Quartus 18.1 lite on windows 8.

 

Is there a better document for getting started with PCIe IP? Just want to simulate and observe the protocol working in Quartus.

 

Thank you very much :)

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7 Replies
AnandRaj_S_Intel
Employee
90 Views

Hi Matt,

 

Looks like working directory is too long. Can you retry after changing the directory length?

 

For document and example refer below links documents

https://www.intel.com/content/www/us/en/programmable/support/support-resources/intellectual-property...

https://fpgawiki.intel.com/wiki/Category:PCI_Express

 

Regards

Anand

 

MMorr23
Beginner
90 Views

I tried shortening the directory to which Quartus restores the .qar file to just "D:/c/", but I still get this error:

 

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016

# Start time: 23:43:27 on Jul 30,2019

# vlog -reportprogress 300 "+incdir+../../common/testbench/+../../common/incremental_compile_module+.." -work work ../../../top_core.vo 

# ** Error: (vlog-7) Failed to open design unit file "../../../top_core.vo" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 23:43:27 on Jul 30,2019, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

# ** Error: D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

# Error in macro ./runtb.do line 115

# D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

#   while executing

# "vlog +incdir+../../common/testbench/+../../common/incremental_compile_module+.. -work work $vfile"

#   ("while" body line 2)

#   invoked from within

# "while {[gets $simlist vfile] >= 0} {

#   vlog +incdir+../../common/testbench/+../../common/incremental_compile_module+.. -work work $vfile

# }"

#   ("eval" body line 3)

#   invoked from within

# "_comp"

 

 

anything else i can try? can you send me the correct top_core.vo file directly?

AnandRaj_S_Intel
Employee
90 Views

Hi,

 

Yes, I have able to replicate the scenario attached modelsim error log.

Let me check and come back.

 

Regards

Anand

MMorr23
Beginner
90 Views

AnandRaj_S_Intel
Employee
90 Views

Still working on it.

we will update you soon.

​Sorry for the inconvenience caused.

MMorr23
Beginner
90 Views

Hi, is there any update? Please help

AnandRaj_S_Intel
Employee
90 Views

​Hi,

 

​Sorry for the inconvenience caused, Still working on it.

 

Meanwhile kindly check below links which have similar issue.

https://forums.intel.com/s/question/0D50P00003yyRkLSAU/how-to-rectify-modelsim-error-failed-to-open-...

 

Regards

Anand

 

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