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15462 Discussions

Error simulating the waveform

Altera_Forum
Honored Contributor II
1,308 Views

Hi guys, 

I've been trying to simulate a VHDL code in Quartus II, but every time I tryed, I got the messages (it is in cap2 file). Anyone knows what these errors means?. 

Just another thing, when I insert my signals to simulate, the program creates one extra position in the matrix, for example I have a matrix(4,7) and the program creates a position (4,0), but the matrix doesn't have it (it is ordened by index 1 to 4, for rows, and 1 to 7, for colums), is that normal?. 

If someone wants to take a look at my code it is in cap3 file.https://alteraforum.com/forum/attachment.php?attachmentid=14749&stc=1  

 

Thanks a lot for your attention! 

https://alteraforum.com/forum/attachment.php?attachmentid=14747&stc=1  

 

https://alteraforum.com/forum/attachment.php?attachmentid=14748&stc=1
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3 Replies
Altera_Forum
Honored Contributor II
121 Views

Hi, 

 

1.Are you using any other file or test bench along with the code you posted? 

There is no error in code i have tried in using Model-sim 10.5b, And i can't see extra bit created during simulation. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)https://www.alteraforum.com/forum/attachment.php?attachmentid=14754
Altera_Forum
Honored Contributor II
121 Views

Hello, 

I'm just trying to simulate it on quartus II, using the automatic test bench generated by the program (I'm using the University Program VWF). 

 

Thanks for your attention!
Altera_Forum
Honored Contributor II
121 Views

What's the point of Gr0 in this code? You just empty it to 0 in both branches of the IF statement.

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