I have a design in AHDL for a keyboard scanner and I'm trying to convert this to Verilog.The AHDL code is in the enclosed ZIP "kbd.zip". The Verilog code is shown hereunder. The line "assign lresult = (sensecount == i) && sense[7 - i];" gives an error that lresult is driven by multiple gates. Anyone an idea how I can solve that? Further remarks about the Verilog code also welcome. Thanks module kbd (sync,advance,mosi,eesel_n,sense,result,drv) ; // Input Port Declarations input sync; input advance; input mosi; input eesel_n; input [7 : 0] sense; // Output Port Declarations output result; output [15 : 0] drv; // Internal variables reg [15 : 0] drvcount; reg [7 : 0] sensecount; wire [15 : 0] ldrv; wire lresult; genvar i; always @(posedge sync) begin if (!eesel_n) drvcount <= 0; else drvcount <= drvcount + 1; end for (i=0;i<15;i=i+1) begin assign ldrv[i] = (drvcount == i); end assign drv = !ldrv; always @(negedge advance or posedge sync) begin if(sync) sensecount <= 0; else sensecount <= sensecount + 1; end for (i=0;i<7;i=i+1) begin assign lresult = (sensecount == i) && sense[7 - i]; end assign result = (eesel_n)? lresult : 1'bZ; // add design description here endmodule
Shouldnt lresult be a 6 bit vector. Otherwise lresult is being driven by each iteration of the for loop.If you didn't know, xilinx ise used to ship with an ahdl to vhdl/verilog translater. Xhdl I think.
Why do you want to convert when AHDL is such a cool language. From Assembly one can move to C++ and discover ease of coding, but from AHDL it is impossible to move out to high level languages. Thanks Intel for continuing to support AHDL.
AHDL does an implied or of multiple assignments to the same variable.So line 47 in kbd.tdf translates to something like this (I don't do Verilog well)
assign lresult = ((sensecount == 0) && sense) || ((sensecount == 1) && sense) || ((sensecount == 2) && sense) || ((sensecount == 3) && sense) || ((sensecount == 4) && sense) || ((sensecount == 5) && sense) || ((sensecount == 6) && sense) || ((sensecount == 7) && sense);But I guess that a simple indexing works as well:
assign lresult = sense;