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Altera_Forum
Honored Contributor I
860 Views

Signal Tap Problem: Some signals have jitter

Dear all, 

I have a 100 Mhz 32 bit width FIFO master interface working on an Cyclone V Altera FPGA. The 100 Mhz fifoclk comes from a connected USB 3.0 interface, which acts as a bridge between the FPGA and a host pc. THe goal of this setup is to investigate the USB 3.0 interface for speed and response timings. 

 

For this I want to look at the data and control signals which are arriving at the FPGA FIFO master and are thrown back to the USB interface. To look at this signal I need to have a sampling clock with at least 200 MHz to satisfy shannons theorem. So I created a 200 Mhz clock which is by a pll and the pll is driven by the cyclone V delopement board (Terasic Cyclone V GX Starter Board) onboard 50 Mhz clock. Between the pll and the signal tap 2 there is also a ALTCLKCTRL to get this clk as global clock working. 

 

However nearly half of the signals which I am looking at are having terrible jitter. I wonder if the problem lies in that the 50 Mhz clock from the devlopment board is not accurately in phase with the 100 Mhz clock from the USB 3.0 interface. But on the other hand even signals which come form the cyclone v dev board are showing this jitter. 

Can you help me investigate this problem? 

 

I also tried so set these clocks as clocks in the sdc but the compiler tells me that they cannot be matched with a port: 

Warning (332174): Ignored filter at al_mc600.sdc(9): clock100_net could not be matched with a port 

Warning (332049): Ignored create_clock at al_mc600.sdc(9): Argument <targets> is an empty collection 

Info (332050): create_clock -name sigClk -period 5.0 [get_ports {clock100_net}] 

Warning (332174): Ignored filter at al_mc600.sdc(11): clk100 could not be matched with a port 

Warning (332049): Ignored create_clock at al_mc600.sdc(11): Argument <targets> is an empty collection 

Info (332050): create_clock -name clk100 -period 5.0 [get_ports {clk100}] 

 

Below is a screenshot of the signal tap signals. For example the signals Data(9:15) can not have such a signal fluctuation until it is first asserted in the near of sample 0. RESET_N must be alway 1 and mem_rstn should also always be 1. :cry: 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14746&stc=1
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4 Replies
Altera_Forum
Honored Contributor I
42 Views

There is no need to drag in Shannon ... 

Just use the 100 MHz USB clock as the clock of your SignalTap system.
Altera_Forum
Honored Contributor I
42 Views

 

--- Quote Start ---  

There is no need to drag in Shannon ... 

Just use the 100 MHz USB clock as the clock of your SignalTap system. 

--- Quote End ---  

 

 

Thank you for your answer. But please can you explain why Shannon is not needed in this case? 

Thank you
Altera_Forum
Honored Contributor I
42 Views

In a SignalTap set-up the same clock that generates the signals is used to sample these signals. The resulting waveform will then resemble what you would see in a simulation waveform. This has nothing to do with sampling as described by Nyquist-Shannon. BTW if you want to apply this to a 100 MHz square wave signal you would need a far higher clock as you have to cover twice the bandwidth of the signal, think of the bandwidth needed for an oscilloscope to display this 100 MHz signal.

Altera_Forum
Honored Contributor I
42 Views

Nyquist-Shannon theorem should be applied when converting analog signal to digital. In your case you already are working with digital signals. So as josyb said no need to involve any theorems here. Jitter that you are seeing is from timing violations (Setup and Hold) which are caused because you are sampling your signals with clock which is asynchronous to them. For signaltap as a sampling clock you have to chose synchronous clock to your signals and thats it.

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