Error using Simulaton waveform editor

Altera_Forum · ‎10-29-2014

Hi, simulating my code I have this problem:

# ** Error: Waveform.vwf.vt(59): near ",": syntax error, unexpected ','

# ** Error: c:/altera/14.0/modelsim_ase/win32aloem/vlog failed.

# Executing ONERROR command at macro ./decoder.do line 4

Error.

In some codes I use (as simple shift registers, sipo, piso) i had similar problems. In others no!

I specify that the codes compilation are always ok.

The code I use is in this case:

--decoder 4 in 16 output

library IEEE;

use ieee.std_logic_1164.all;

entity decoder is

port (

in_sel : in std_logic_vector (3 downto 0);

output : out std_logic_vector (7 downto 0)

);

end decoder;

architecture decoder_arc of decoder is

begin

A: process (in_sel)

begin

case in_sel is

when "0000" => output <= "00000001";

when "0001" => output <= "00000001";

when "0010" => output <= "00000010";

when "0011" => output <= "00000010";

when "0100" => output <= "00000100";

when "0101" => output <= "00000100";

when "0110" => output <= "00001000";

when "0111" => output <= "00001000";

when "1000" => output <= "00010000";

when "1001" => output <= "00010000";

when "1010" => output <= "00100000";

when "1011" => output <= "00100000";

when "1100" => output <= "01000000";

when "1101" => output <= "01000000";

when "1110" => output <= "10000000";

when "1111" => output <= "10000000";

end case;

end process A;

end architecture;

I attach the project.

Thanks for your attention!

Altera_Forum · ‎10-29-2014

This is not the code the error relates to - the error is some incorrect syntax in the waveform file.

Altera_Forum · ‎10-29-2014

Btw, your VHDL is syntaxtically wrong as you have not included an others choice in the case statement.