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Error: (vsim-3173) Entity '...' has no architecture.

AvramG
Beginner
2,221 Views

Hi.

 

I intend to work on Cyclone10 chip. I try to do a simulation on 1-port RAM IP in Questa. 

When I run my compile_async_player.do file with the following commands:

 

vcom -stats=none -work work -2008 -explicit -vopt ./async_input_bram_player/async_input_bram_player_tb.vhd
set TOP_LEVEL_NAME async_input_bram_player_tb
set QSYS_SIMDIR ./async_input_bram_player/async_input_bram_player/sim
source $QSYS_SIMDIR/mentor/msim_setup.tcl
ld_debug

 

I get the error message:

# Loading work.async_input_bram_player_tb(testbench)#1
# ** Error: (vsim-3173) Entity 'C:/svn/exo_r_c10gx/simulation_bad/libraries/work.async_input_bram_player' has no architecture.

 

Attached are 2 zip files with 2 similar projects:

"simulation_bad"  - not working

"simulation_good"  - working

 

The difference between the 2 projects (bad and good) is the project path (of the compile_async_player.do file and libraries location).

 

I think the problem is the libraries folder, but I don't know how to change it.

 

thanks in advance.

 

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4 Replies
ShengN_Intel
Employee
2,039 Views

Hi,


After I replace the simulation_bad file msim_setup.tcl script with the one in simulation_good file,  simulation_bad file can be simulated properly.


Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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AvramG
Beginner
1,999 Views

Hi Sheng,

Thanks for your help.

I replaced the msim_setup.tcl file and I got the same eror:

# Loading work.async_input_bram_player_tb(testbench)#1
# ** Error: (vsim-3173) Entity 'C:/svn/exo_r_c10gx/Altera_community/simulation_bad/libraries/work.async_input_bram_player' has no architecture.

 

Could you upload your simulation_bad directory (after the fixing)?

I want to compare with mine.

Best regards,

Avram

 

 

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ShengN_Intel
Employee
2,025 Views

Hi,


Any further update on this thread?


Thanks,

Best Regards,

Sheng


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ShengN_Intel
Employee
1,979 Views

Hi Avram,


I didn't change anything in your simulation_bad file. I just simulate it with questa starter edition and then I got different error as below:

Fatal: (vsim-3693) The minimum time resolution limit (1ps) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

Then, I replace msim_setup.tcl in simulation_bad file with the one in simulation_good file and everything finally work fine.


Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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