Error while executing: Force

[Altera_Forum]

Hello all, 

 I recently installed ModelSim, and am having all sorts of issues with it. I am trying to simulate a project that contains several Altera IP cores (counter, ROM, PLL, ALTDIDO) and am having no luck. I am running Analysis and Synthesis on the design, and then Tools->Run Simulation Tool->RTL Simulation. ModelSim starts, but I do see a few errors in the Transcript: # ** Error: C:/altera/15.1/modelsim_ae/win32aloem/vlog failed.# Error in macro ./DACSimulation_run_msim_rtl_vhdl.do line 12# C:/altera/15.1/modelsim_ae/win32aloem/vlog failed.# while executing# "vlog -vlog01compat -work work +incdir+D:/Users/[username]/Desktop/Research/Quartus\ II/January\ 2016/1_28_2016/dac {D:/Users/[username]/Desktop/Research/Q..."  In addition, there are two 'suppressible' errors about names already being declared in this scope (I don't think these are causing issues).  So, in my new simulation, I go to Library->work, and I see several of my IP cores. However, if I right click on them and select Simulate, I get an error:  vsim work.ALTDDIO_CLK_OUT# vsim work.ALTDDIO_CLK_OUT # Start time: 14:52:13 on Feb 15,2016# ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.# Error loading design# End time: 14:52:13 on Feb 15,2016, Elapsed time: 0:00:00# Errors: 0, Warnings: 0  I'm not sure what I'm having license issues. I have a modelsim license *.dat in the installation directory. So, instead I right click on the IP instantiation and Create Wave. However, if I right click on a signal and select 'Clock', I get another error:  force -freeze NewSig:/ALTDDIO_CLK_OUT/dataout 1 0, 0 {500 ps} -r 1000# Error while executing: force# Usage: force <object_name> {<value> [[@]<time_info>][, <value> [[@]<time_info>]...} [-freeze | -drive | -deposit] [-cancel [@]<time_info>] [-repeat [@]<time_info>]  Can someone help me get my simulation working?

[Altera_Forum]

Im guessing you dont have a dual language capability in your licence. The cheaper versions of modelsim only have single language capabilities.

[Altera_Forum]

--- Quote Start ---  Im guessing you dont have a dual language capability in your licence. The cheaper versions of modelsim only have single language capabilities.  --- Quote End ---    Is there an easy way to verify that this is the cause? Can I 'view' the license for ModelSim? If I did all of my work in Verilog, does that mean the IP cores (if this is the issue) are all, by default, VHDL? Is there a way to convert them to verilog?

[Altera_Forum]

Usually you get the choice of what language to generate the core in. 

If you have the free edition of modelsim, then you dont have dual language licence.

[Altera_Forum]

--- Quote Start ---  Usually you get the choice of what language to generate the core in. If you have the free edition of modelsim, then you dont have dual language licence.  --- Quote End ---    I am not using the free edition. Or at least, if I am, it is not intentional. I have a license to the software.  Help -> About: ModelSim ALTERA 10.4b  My license is for "MODEL SIM ALTERA EDITION".

[Altera_Forum]

The Licence you have is the free one that comes with modelsim altera edition and is not able to simulate mixed language designs. 

The version of modelsim that ships with Quartus 15 is able to do mixed language.

[Altera_Forum]

--- Quote Start ---  The version of modelsim that ships with Quartus 15 is able to do mixed language.  --- Quote End ---    Hmm, I guess I don't have that license then. I do have a license for Quartus II Standard Edition though, and just reaffirming, that doesn't help me at all?     --- Quote Start ---  The Licence you have is the free one that comes with modelsim altera edition and is not able to simulate mixed language designs.   --- Quote End ---    The two IP cores that appear to no have a verilog option are LPM Counter and ROM 1-Port. Are there alternative IP cores that have a verilog option, or can I simply not sure those?  EDIT: Recreating the cores (they were originally created I think in QII v12 as verilog seems to have allowed me to output verilog black box files. I'll give those a go.

[Altera_Forum]

--- Quote Start ---  Hmm, I guess I don't have that license then. I do have a license for Quartus II Standard Edition though, and just reaffirming, that doesn't help me at all?    --- Quote End ---    All you need to do is download and install Q15.  Counters and roms are very basic units and can be infered from written HDL. They dont need to be generated.

[Altera_Forum]

--- Quote Start ---  All you need to do is download and install Q15.  --- Quote End ---    I am launching ModelSim from Quartus Prime 15.1 already using Tools->Run Simulation Tool->RTL Simulation. Do I need to do something differently?  Also, I've checked that all of my IP components have a *_bb.v Verilog HDL black-box file as their output. However, I am still having the same licensing issues when I launch ModelSim from Quartus. Perhaps I have two versions of ModelSim and Quartus is launching the wrong one? I only see ModelSim-Altera Edition installed on the machine, however (v15.1.0.185).

[Altera_Forum]

Is it your suggestion I uninstall both ModelSim and Quartus, and then reinstall Quartus, and that should 'come' with an install of ModelSim? And that version of ModelSim should work? I thought I had removed anything that had VHDL code in it, but maybe I missed some? If there are any files that are VHDL but *not* in the design (but included in the project), will that cause any hangups? I don't see any VHDL files in project.

[Altera_Forum]

You can install multiple version of quartus and modelsim on the same system. and they will all work.

[Altera_Forum]

So, I've cleaned out anything that was VHDL in the project, including some old vhdl.do files. Additionally, I renamed anything in the path of the project/simulation that had spaces in the directory name. Now, it appears there are no errors on startup of ModelSim. However, if I select "simulate" on one of the IP cores in my design, I get the following: 

 ModelSim> vsim work.TX_PLL_altpll # vsim work.TX_PLL_altpll # Start time: 16:40:32 on Feb 22,2016 # ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog. # Error loading design # End time: 16:40:32 on Feb 22,2016, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0  Do you still think this is a VHDL error? Is there any way I can find the offending vhdl file so I can remove it?

[Altera_Forum]

You may need to contact your FAE or Altera or Mentor about this problem.