Error with the DDR SDRAM generated

[Altera_Forum]

I am using DDR SDRAM controller in SOPC builder, when compiling the project with QuartusII following error appears. My FPGA is EP2S60F672C3. 

 Any help on how to resolve this.   Error: Atom "ddr_dqs_to_and_from_the_ddr_sdram[1]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true Error: Atom "ddr_dqs_to_and_from_the_ddr_sdram[0]" has port DQSUPDATEEN that must be connected to the dqsupdate output of a DLL because the dqs_ctrl_latches_enable parameter is set to true Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 200 warnings Info: Allocated 218 megabytes of memory during processing Error: Processing ended: Sun Nov 29 15:27:00 2009 Error: Elapsed time: 00:01:13       Thanks , hquanlin

[Altera_Forum]

Basically you've got a DDR controller but the DQS ports of the controller are not connected to the dedicated DQS pins on the Stratix II device. 

 Reasons for this: 1 - You haven't made pin assignments. 2 - You haven't actually connected the ports to the pins in your logic. 3 - You haven't connected all of the ports on the DDR controller to something useful and the logic for the datapath is being synthesized away.  Jake