Dear all,
I have difficulties to simulate my design for a PLL reconfiguration. I followed the procedure by implementing a wrapper around the PLL and PLL reconfig.
Problem is that during simulation, I see the busy signal coming from the PLL reconfig (from megawizard) having an undefined state. The procedure to reprogram the PLL is then not performed.
Has a behaviour model have been describe for this?
I am using ncvhdl to compile.
I think I have added the correct library to be able to compile the PLL block (pll conf, and reconf) i.e. :
ncvhdl -v93 -cdslib ./cds.lib -hdlvar ./hdl.var -linedebug -mess -work altera_mf
$CADHOME/.caddata/quartus/eda/sim_lib/altera_mf_components.vhd
$CADHOME/.caddata/quartus/eda/sim_lib/altera_primitives_components.vhd
$CADHOME/.caddata/quartus/eda/sim_lib/altera_mf.vhd
$CADHOME/.caddata/quartus/eda/sim_lib/altera_primitives.vhd
ncvhdl -v93 -cdslib ./cds.lib -hdlvar ./hdl.var -linedebug -mess -work stratixii
$CADHOME/.caddata/quartus/eda/sim_lib/stratixii_atoms.vhd
$CADHOME/.caddata/quartus/eda/sim_lib/stratixii_components.vhd
It compiles fine, but during elaboration it tells that this component is not fully bound:
cntr1 : lpm_counter which is part of the PLL_reconfig block generated by the megawizard.
I have no influence here, I wonder if my libraries are correct. I am using the version 9.0 of quartus, and libraries came with it.
It finds the component in the libraries bu apparently the are no defined the same way...
Any tips to help me out with this?
Thanks ahead for your time and attention
